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RE: LF: Re: Re: FET RDS

To: "[email protected]" <[email protected]>
Subject: RE: LF: Re: Re: FET RDS
From: Rik Strobbe <[email protected]>
Date: Thu, 13 Jan 2011 20:19:16 +0100
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Thread-topic: LF: Re: Re: FET RDS
Andy,
 
I agree.
I just had a look in experiment logbook. In 2002 I did build a 137kHz class E PA using a single IRF640 and got 255W output at 56V and 4.9A input (= 275W input), so efficiency was almost 93%. Initially efficiency was much lower (85%) mainly caused by the inductances. After rewinding them it was OK.
For comparison: my push pull class D PA (clone of the G3YXM design)  had an effiency of 86% on 137kHz (430W out at 56V / 8.9A). Later I modified this PA to 500kHz where I get 80% effeciency (350W out at 56V / 7.8A). Again a significant part of the losses are in the coils of the LPF that get quite hot in QRSS mode or after longer CW transmissions.
 
73, Rik ON7YD - OR7T

Van: [email protected] [[email protected]] namens Andy Talbot [[email protected]]
Verzonden: donderdag 13 januari 2011 18:55
Aan: [email protected]
Onderwerp: Re: LF: Re: Re: FET RDS

If I can get 80% for 400V on 500kHz using a pair of cheap and cheerful FETs cobbled together, 90% plus should be easy-enough by spending a bit of time and effort on their selection.   
A while back I managed greater than 85% on a 20W class E topband PA, and that is an overall efficiency figure,  including power taken by driver stages and dropped in linear regulators. 
So its hardly rocket science.
 
Andy
 


 
On 13 January 2011 17:44, mal hamilton <[email protected]> wrote:
Jim
What you say is correct but it is virtually impossible to achieve the 90%
plus efficiency claimed by some. The FET required in practice is not
available and these high efficiencies are only theoritical.
I have found this in practice ie 80% if you are lucky on a good day
mal/g3kev


----- Original Message -----
From: "James Moritz" <[email protected]>
To: <[email protected]>
Sent: Thursday, January 13, 2011 5:31 PM
Subject: LF: Re: FET RDS


> Dear Mal, Andy, LF Group,
>
> There is a trade-off in construction of MOSFETs - basically, for a given
> area of silicon,  higher BVdss requires a thicker active region of the
> MOSFET with higher on resistance. You can reduce Rdson by using a greater
> chip area, but that means higher capacitances, increased cost, etc. So you
> can't have your cake and eat it.
>
> In Andy's breadboard circuit, there is a mismatch between the available
> MOSFET type and the available PSU voltage - the 500V BVdss is a bit too
high
> for a 60V DC supply - the peak voltage in an ideal class E is 3.56 x Vdc,
> perhaps you would allow 5 x Vdc for safety. 300V BVdss mosfets seem a bit
> thin on the ground, so more efficient schemes might be to increase Vdc to
> about 100V, or reduce it to about 40V and use lower Rdson 200V mosfets.
>
> Cheers, Jim Moritz
> 73 de M0BMU
>
>
>



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