Jim
What you say is correct but it is virtually impossible to achieve the 90%
plus efficiency claimed by some. The FET required in practice is not
available and these high efficiencies are only theoritical.
I have found this in practice ie 80% if you are lucky on a good day
mal/g3kev
----- Original Message -----
From: "James Moritz" <[email protected]>
To: <[email protected]>
Sent: Thursday, January 13, 2011 5:31 PM
Subject: LF: Re: FET RDS
> Dear Mal, Andy, LF Group,
>
> There is a trade-off in construction of MOSFETs - basically, for a given
> area of silicon, higher BVdss requires a thicker active region of the
> MOSFET with higher on resistance. You can reduce Rdson by using a greater
> chip area, but that means higher capacitances, increased cost, etc. So you
> can't have your cake and eat it.
>
> In Andy's breadboard circuit, there is a mismatch between the available
> MOSFET type and the available PSU voltage - the 500V BVdss is a bit too
high
> for a 60V DC supply - the peak voltage in an ideal class E is 3.56 x Vdc,
> perhaps you would allow 5 x Vdc for safety. 300V BVdss mosfets seem a bit
> thin on the ground, so more efficient schemes might be to increase Vdc to
> about 100V, or reduce it to about 40V and use lower Rdson 200V mosfets.
>
> Cheers, Jim Moritz
> 73 de M0BMU
>
>
>
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