Hello Andy,

Thanks for that! Bearing in mind i am not the sharpest knife in this
drawer,  would  that  perhaps explain  why the U3S Si5351a output drives more
reliably at 3.3V  than  say the output of a doubler / pre amp (and I was never
happy  about  the  pre amp output level being correct...), and perhaps
the  output  from the squarer also being more "reliable"? Would you be
able to sketch an interface design to try please? Thanks again, are we
getting somewhere? ;)

Tuesday, February 26, 2019, 4:38:15 PM, you wrote:

> AH - HA !!!!!!!!!!!!
> Therein may lie your problem.   If you take your input direct to
> the 74F74 clock and don't hit that with anything other than a square
> wave you are bound to have problems.   TTL devices (and F series
> really IS real TTL) get very unhappy with slow edges and can
> oscillate or show instability at the edges


> Even if you precede that with the classic inverter and linearising
> resistor, at low frequencies you will often see instability.   That
> fed-back gate design usually works fine at tens of MHz and up, even
> MHz, but expect instability at kHz frequencies.   Look at the output
> on a scope, and don't be surprised to see ringing on the edges ,
> especially at low drive levels, and low drive levels are just what
> you get when the input waveform is keyed on / off


> At these frequencies, linear to logic conversion really MUST be
> done with a Schmitt trigger.   74xCT14 or similar.   Use the ACT or
> HCT families as opposed to the HC or AC ones as they have a smaller
> hysteresis between Vin(HI) and Vin(lo), allowing for lower amplitude
> drive.  They also need different centre biassing for AC coupled
> signals.  Assuming a 5V rail, Use 2.5V  for HC and AC families,  1.8V for ACT and  HCT devices.


> Or an RS422 / RS485  line receiver works well; that has even lower
> hysteresis and hence lower permitted drive level.


> Andy
> www.g4jnt.com




--
Best regards,
 Chris                            mailto:[email protected]