Return to KLUBNL.PL main page

[Top] [All Lists]

Re: LF: Class E PA

To: [email protected]
Subject: Re: LF: Class E PA
From: DK1IS <[email protected]>
Date: Tue, 9 Oct 2018 12:40:43 +0200
Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed;; s=mail; t=1539081469; bh=NILMYt9Pie+Haoj8CZhfJHGvRPpg4iRZQkoB5lwdLnw=; h=Subject:To:References:From:Date:MIME-Version:In-Reply-To: Content-Type; b=oRBTNwiiSCIUGWpQ6moufYhtww82oDz4/3OistTkY7PruZgocgxOn0p8ws345iUtb 1yWuhz2Tpk/7UMjCnIWzPSWUS/h9Ykm0dkB/XVtXuieywNGQ2ebdGux8hJqTXnnzo4 q/0eLW7UKHTnDULOBat+/G4vdYL77eOHlPkNifc8=
In-reply-to: <[email protected]om>
References: <[email protected]> <[email protected]om>
Reply-to: [email protected]
Sender: [email protected]
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1
Hi Riccardo,

thanks for the link - I prefer the most basic version. But like in all other papers I know the problem of the first positive drive pulse after applying the DC power is ignored - perhaps because Class E is mainly discussed for frequencies from MF upwards with correspondent low shunt capacitors. With some hundreds of pF the current peak should be limited by the parasitic impedances but at VLF you get values in the uF range, see attached design sheet from , Version 2.08, describing my plan. Looking at the so far replies I think it would be the best to key the DC voltage synchronously to the next positive drive pulse. In the steady-state condition this topic is no longer relevant, but then the FET could already be dead ;-)

Tom, DK1IS

Am 08.10.2018 um 23:21 schrieb Riccardo Zoli:

Hi Tom,

Which class E configuration did you choose? See the attachment (extracted from Anyway, i think the shunt capacitor it will be much lower than you expected but it depends on the number of paralleled MOSFETs (if necessary).

73 de Riccardo IW4DXW

Il Dom 7 Ott 2018, 19:52 DK1IS <[email protected]> ha scritto:

Hello Group,

Planning a new single-ended Class E PA for my activities on the Dreamers Band (8.27 kHz) two questions came up - perhaps someone can help me:

-  Being interested only in on-off-keying I´m concerned about the capacitor in parallel to the power FET which in my case on VLF will be in the uF range. If the DC supply is on and without gate drive this capacitor is charged to the DC supply voltage. At the first positive gate pulse it discharges via the drain-source-path, the current being  limited only by parasitc impedances - a poorly defined condition which usually has to be avoided. Does this mean that I have to apply drive continously and key the DC power supply only, perhaps synchronously to the next positive drive pulse?
Is there any rule of thumb for the inductance of the rf choke in the drain-power supply path?

Thanks for any idea!

Tom, DK1IS

Attachment: ClassE Tonne.pdf
Description: Adobe PDF document

<Prev in Thread] Current Thread [Next in Thread>