Hi Riccardo,
thanks for the link - I prefer the most basic version. But like in
all other papers I know the problem of the first positive drive
pulse after applying the DC power is ignored - perhaps because
Class E is mainly discussed for frequencies from MF upwards with
correspondent low shunt capacitors. With some hundreds of pF the
current peak should be limited by the parasitic impedances but at
VLF you get values in the uF range, see attached design sheet from
www.TonneSoftware.com. , Version 2.08, describing my plan. Looking
at the so far replies I think it would be the best to key the DC
voltage synchronously to the next positive drive pulse. In the
steady-state condition this topic is no longer relevant, but then
the FET could already be dead ;-)
73,
Tom, DK1IS
Am 08.10.2018 um 23:21 schrieb Riccardo Zoli: