Re: LF: Ramped BPSK

[Andy Talbot <andy.g4jnt@gmail.com>]

You can just about get away with clocking the DDS directly for 137kHz.    With and additional divide by 16, your DDS has to produce 2.2MHz which is within the capability of a DDS running at 10MHz clock.   Just use a decent 5th or 7th order LP elliptic on its output and you can generate up to 3MHz from a 10MHz clock

Then your step size will be 10E6 / 2^32 / 16 = 146uHz, and your accuracy worst case, half that at 73uHz

Andy

On 14 November 2015 at 20:47, <jcraig@mun.ca> wrote:

Hi Andy,

I was about to solder a dpdt relay across a transformer until I saw your posting.  The DDS here is the 9851 and the 40 bits are loaded serially.
If bits 35-39 are changed from 00000 to 00010 the phase will change by
180 degrees and so the soldering iron can be switched off?

An AD9852 would spare me the humiliation of being a significant
part of a mHz off QRG, but these chips seem hard to get.  Markus was
right about the resolution. The DDS is clocked at 10 MHz with the
x6 multiplier. The output is then divided by 16.  The resolution is just
under 1 mHz and so the frequency error depends on the output frequency.

73 Joe VO1NA



On Sat, 14 Nov 2015, Andy Talbot wrote:

Try the Anlaog Devices web site - www.analog.com

I built my own PCB,   http://www.g4jnt.com/AD9852module.pdf   (PCBs are no
longer available for that, though).  That particular DDS is a bit out of
date now.  I use it  for this job as I have a few modules left, and it is
one of the few devices  with both a 48 bit frequency setting register and
amplitude programmability.

Andy  G4JNT

On 14 November 2015 at 19:20, Paul Nicholson <vlf0403@abelian.org> wrote:

With sufficiently brief phase steps, those discrete sidebands
will fall outside the loading coil bandwidth and be well
attenuated.

But, does that bring back the audible clicks from the PA
and coil?

I'm keen to have a play with these DDS chips.  Is there a
recommended evaluation board?

--
Paul Nicholson
--