To: | [email protected] |
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Subject: | Re: LF: Coherent BPSK on LF using EbNaut |
From: | Andy Talbot <[email protected]> |
Date: | Fri, 2 Oct 2015 15:07:21 +0100 |
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I know when to give up a poor job! I built a nice dual 100Hz LPF and coherent 12 bit digitiser sampling at 800Hz. Formed the results into packets to send to a PC, Wrote some software for the PC that read the data and plotted a vectorscope, phase, amplitude etc. Was almost about to build in an FFT It all worked very well with a baseband input for testing I got a Finningley Dongle QSD receiver (very similar to the Softrock) and modified that for LF input with a 500kHz LPF and removed the caps to allow a DC coupled output. Fed my 2.5V reference derived from the A/D converter reference back to that as its 2.5V centre rail so everything was centred around a common reference But I've been having all manner of problems with the DC offset changing and although it can be made to work - sort of, results are messey. The DC offset even changes with input termination impedance So much so I've lost patience - especially as I had a sudden realisation....... Having two SDR-IQ receivers I'm prepared to hack about with one of them. Although they have an option for an external clock input, I've never tested it. So inserted the external clock input socket, disabled its own XO and got that working. Discovered the clock input can happily be 64MHz so long as you tell the software what it is, or 66MHz, or values near there. Unfortunately 60MHz doesn't work, and 70MHz is not allowed, so a simple direct multiplication from a 10MHz reference isn't possible However, a simple PLL locked at 65MHz or any integer 1 or 2MHz multiple between say 62 - 69MHz should do. That will give a coherent locked receiver, and the software already is geared up for SDR-IQ interfacing. Andy G4JNT On 2 October 2015 at 03:56, Paul Nicholson <[email protected]> wrote:
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