Hi Chris,
Can you exclude that this is a driver issue? Because then it is a
different story. If the PA is hard keyed, always with a proper waveform
(pulsewidth), then i expect no problems.
For the problem discussed, i think that the currents are limited by the
on-resistance, the inductance of the loop between the components and by
the internal resistance of the capacitor. As soon as the current starts
to flow, the voltage of the cap will drop, so this will lower the peak
current (i.e. it is not the voltage of the cap divided by the
on-resistance only). The peak current may be 100 A, but just for some 10
us. And the strong FET will handle this.
73, Stefan
PS: I remember i had similar problems on LF. But that was a driver
issue, a wrongly built up comparator circuit.
Am 14.10.2018 11:00, schrieb Chris Wilson:
Hello DK7FC,
The biggest voltage and current spikes in my W1VD Class d amp are when
a WSPR or OPERA transmission ceases, from back EMF I presume.
I am curious as tvo whether a "soft voltage start" circuit could be devised
and added to other power supplies similar to the one discussed
earlier?
Sunday, October 14, 2018, 9:30:20 AM, you wrote:
Hi Tom,
Good luck with your PA.
Tell us the component values when you're finished, as well as the
actual efficiency. From my LF PA i remember the coil, which was
quite large already ('air-cored').
Regarding current peaks at the first switching: I would simply
ignore the problem and see if the FET will survive (and how old it
becomes). If it's lifetime is actually to short, then i would start
thinking about a solution for the problem. One of them just costs 2
EUR or so, so it is worth to try...
73, Stefan
Am 14.10.2018 00:16, schrieb DK1IS:
Hello group,
Just to close this thread:
Concerning the problem of the first drive pulse with DC power
already on: Bob, W1XP, made an important contribution in a private
mail. He pointed out that the current spike I was worried about
would be limited by the FETs output characteristic anyway. Looking
to the data sheet of my intended IRFB 4227 this seems to be true
although there could persist a certain limitation by the save
operation area. Perhaps I was a little bit too naive estimating the
peak current as Vdc / Rdson ... Be that as it may, using the newly
discovered DC soft start feature of my power supply should overcome
this challenge. Controlled by a logic level input it runs up the
output voltage with a time constant of about 100 ms. This will
protect the FET, avoid any key clicks and won´t affect the
readability of the long lasting vlf signals. To keep the signal
phase constant (essential on vlf) oscillator and gate drive of the FET won´t be
keyed at all.
I´ve just modified the antenna / loading coil system to resonate at
8270 Hz without transformers, - 3dB band width now being 168 Hz.
Including 25 m RG213U from the arbour to the shack (being later on
part of the matching network) the feeding impedance is now 480 Ohms
pure resistive which will be matched to the rest of the class E PA
by its output network. Thus I`m able to omit the two matching
transformers being used up to now, see www.qrz.com/db/dk1is.
Now I´m waiting for the driver ICs coming from China - in Germany
up to now without additional tax ;-) !
Thanks for all the feedback, 73,
Tom, DK1IS
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