Re: LF: FET driver driven direct from a Si5351a questions

[David Bowman <davidg0mrf@gmail.com>]

Hi Chris.

Not sure I have a solution for the circuit you have. 

However, it may be worth not using the 180 degree outputs from the Silab oscillator.  Have you thought about the advantages of a FET driver

that has a common input but 2 antiphase outputs ??

The TC4428 is an example. They take great care with rise times and propagation delays....perhaps the Si device does not give 'perfect' waveforms.

Worth a try ??

regards

David

On Wed, Oct 10, 2018 at 2:23 PM Chris Wilson <dead.fets@gmail.com> wrote:

Hello LF'ers,

Hi, bit of an oddball problem here (again.... ;)) I have
a 1kW Class D low frequency 137 kHz LF ham band amp I built. It has
worked fine for many months. I like experimenting /
learning /simplifying so when the designer of the QRP Labs U3S exciter
I am using added some new firmware features I decided to try and take
advantage of it. The U3S is based around a SiLabs Si5351a synthesizer
chip. Originally I had the U3S send out a X2 frequency from CLK0 alone
as the amp, a Class D device, halved it. (None of the circuitry after
the CLK0 and CLK1 outputs in the U3S is used, the Si chip *IS* the
exciter with no amplification as shown on the U3S schematic from the
BS170(s), in fact these components are not even fitted).

 The new firmware allowed me to delete one IC (the 74F74) and the 5V
 regulator and drive the FET driver IC at X1 frequency with the
 outputs from CLK0 and CLK1 of the Si5351a set to be 180 degrees out
 of phase. Before this firmware feature addition I used just CLK0 at
 X2 and the 74F74 IC did the division and phasing and its output drove
 an IR2110 FET driver IC. I swapped to an MCP1404 driver IC so I could
 delete the 5V regulator as well.

What is happening is with no voltage to the amp's FET drains the gate
waveform is excellent. but as soon as even 5V is applied to the drains
the gate waveform goes ragged and drain waveforms go HORRENDOULSY
spiky.

With  the  original  setup  the gate and drain waveforms (gates at the
bottom) look fine to me:

http://www.chriswilson.tv/inverted/good-gate-and-drain-waveforms.jpg

I also see seemingly random ultra short duration drop outs in
the square waves from CLK0 and CLK1. These ultra brief glitches occur
on CLK0 and CLK1 even when nothing is connected to them save my X10
scope probes. This suggests a firmware issue to me, but I may be
missing something like impedance matching? This is also apparent
whilst it is transmitting the digital mode WSPR from the U3S. Can
anyone think of a reason for this please?

It may be that the very infrequently used firmware option to have the
Si5351a output on both CLK0 and CLK1 with a 180 degree phase shift is
buggy, in which case I am solely at the mercy of the designer, but I
want to be sure I am not missing anything before assuming this to be
the case. I have also been told that it may be that the Si5351a
produces less than perfect waveforms below about 3 MHz when the
outputs are inverted, but no source for that was cited. So the changes
from working perfectly to problematic are using a 180 degree phase
shift from both CLK0 and CLK1 adding two 82k resistors to the 12V rail
to bias the input pins of the MCP1404, and using the MCP1404 instead
of the IR2110 which needed a 5V supply as well as 12V.

If you are still with me, thank you!

http://www.chriswilson.tv/inverted/amp-less-surplus-controls.jpg

http://www.chriswilson.tv/inverted/amp-simplified6.jpg

http://www.chriswilson.tv/inverted/u3s-schematic.jpg

http://www.chriswilson.tv/inverted/no-drain-voltage.jpg

http://www.chriswilson.tv/inverted/with-drain-voltage.jpg



--
Best regards,
 Chris                          mailto:dead.fets@gmail.com