Re: LF: W1VD amp help

[Andy Talbot <andy.g4jnt@gmail.com>]

In my half-bridge 700 Watt design, http://www.g4jnt.com/137tx.pdf  I used a small inductor between the top and bottom FETs to absorb the energy from any short glitch when both devices are on.   In a transformer push-pull like that I'm not sure how you'd implement exactly that idea, but a small L in each drain may suffice.   Saves having to complicate the drive waveform with a deliberately induced dead zone.

Andy  G4JNT

On 8 April 2018 at 12:53, N1BUG <paul@n1bug.com> wrote:

Jay,

Thanks for the detailed response! See below, threaded in.

> HP3325A ... set frequency x2, square wave, amplitude 5 volts, dc
> offset 2.5 volts. Have used the HP3325A here for countless numbers
> of years.

Done, verified that it looks OK with scope. (Previously I had not
been testing with the DC offset!)
  
> Always start out on the dummy load.

I've reduced drain voltage to 13V so that I can do that. I have no
dummy load which can handle the next step up (25V). No one near me
does either.

> Test in stages. Test the driver
> into the FETs with the FET drain supply off. Verify the waveforms
> with a dual trace scope to see that there's a small 'dead zone'
> between the two phases.

There is a delay between one phase beginning to switch off and the
other phase beginning to switch on, but I am not sure I would quite
call it a 'dead zone'.

Sorry about the quality of images. Scope 5V/div.

Gate waveforms:

http://www.n1bug.com/gates1.jpg

With the traces overlaid and time stretched out so you can better
see the crossing between phases:

http://www.n1bug.com/gates2.jpg

It appears one has not fallen to zero by the time the other one is
coming up. Should it?

> Once the gate waveforms are confirmed to be correct,

I've paused testing at this point pending any comment on my gate
waveforms or request to repeat with different settings.

Paul