Re: LF: Softrock RX divider IC problem, unexpected frequency out

[Andy Talbot <andy.g4jnt@gmail.com>]

I never documented the mods made to my Softrock [clone] to get it down to low frequencies, so took a look inside to see what I did.   I see I used an LM393 comparator and it took a few minutes to realise why I did that instead of a Schmitt biassed half way as suggested here.

I am deriving my LO from a DDS source, an AD9852, which only delivers about 2 V p-p.   This was not enough to reliably swing between the thresholds of a 74AC Schmitt which lie roughly at  1.5 and 3.5 Volts.   The LM393 has a much lower hysteresis of around 400mV so worked with lower input.   I wanted to get it down to 5kHz RF (20kHz LO input).

As you will be using the Q2 buffer, there should be no problem getting a 2.5V to 3V swing for hitting the Schmitt thesholds.

Andy  G4JNT

On 27 January 2018 at 16:49, Andy Talbot <andy.g4jnt@gmail.com> wrote:

Looking at the schematic, I see a 74AC74 divider is used which works at over 100MHz clock frequency.   You are hitting its edge triggered clock inputs with low frequency waveform (461kHz) with  a slow and indeterminate rise time caused by crude semi-linear amplification plus clipping.   It really is no wonder the system is not driving the divider properly.    That sluggish edge has to hit the D input on both flip-flops and cause them to toggle together.   I'm surprised it even appears to work at HF where the design originated.

That design with no proper logic level squarer is just asking for trouble and I'd be surprised if you ever get it to work properly.  It might, perhaps, if the divider were changed to a slower 74HC74 device, but that's a bit speculative;  it may be just as bad.

 I would suggest you stop fiddling about with component values, trying to frig an unsuitable design.  You MUST feed  a proper shaped logic level to such high speed divider chips.  There really is no getting round that fact.  They won't work properly otherwise - just look at the specifications for AC series logic.

You can keep the simple single transistor buffer, but use its output to feed the input of a shaping gate.  A Schmitt like a 74HC14 (a package that has 6 suitable gates) ought to do you nicely.    Bias the input mid way between its two threshold voltage - these are different for HC and HCT family devices, so consult the data sheet.  AC couple your RF to the mid-biassed input and connect output to the divider.      Look at the gate output on a scope and you'll have a beautiful square wave width lovely vertical edges and perfect quadrature generation however low a drive signal you put in.

Andy  G4JNT

On 27 January 2018 at 16:13, Chris Wilson <dead.fets@gmail.com> wrote:

Hello all.

Today  when powered up there was rarely any output from the divider at
all, so I started again.

I decided to try two things, build a little test rig with a spare xtal
of the same 461.5kHz as the one in the RX with the same C10 at 3900pF
and C11 at 2700pF on a bit of pcb and excite it at 1v P to P sine wave
from my sig gen around the xtal frequency and look at the output on
the scope. That failed abysmally, no change in display, thinking about
it maybe it's due to the big capacitances involved?

Anyway, back to the RX. C12 at 680pF, C10 at 3900pF and C11 at 2700pF.
Waveforms taken with scope at DC coupling, but V scaling changes. I
believe (dangerous with my lack of knowledge..) that C10 to base of Q1
is good. Base of Q2 looks ok. But with R16 at the recommended 10K I
see half a sine wave at the emitter of Q2. With the original 20k (I
don't have the oddball 20.1k around) the waveform is still part
complete and of a much lower amplitude.

Is this a bias issue with Q2 or something else please?



I  hope  the file names are self explanatory! Note that V axis scaling
changes in some shots!!


Thank you for all your help!





The schematic for the modded Softrock Lite II in question:

      http://www.gatesgarth.com/schematic2.jpg


 Scope screen captures:

  http://www.gatesgarth.com/lf-base-q1.jpg

  http://www.gatesgarth.com/lf-emitter-q1.jpg

  http://www.gatesgarth.com/lf-base-q2.jpg

  http://www.gatesgarth.com/lf-emitter-q2-r16-at-10k.jpg

  http://www.gatesgarth.com/lf-emitter-q2-r16-at-22k.jpg


Friday, January 26, 2018, 11:52:20 PM, you wrote:

> Hi again


> Well all seems well if you are getting a good wave at the flip flop
> output. Just a comment about your input wave forms yes the MF does
> show a second harmonic petty low and as you have said the MF version
> works OK. Please remember a square wave is in fact and infinite
> number of harmonic frequencies so this is not an issue the dominant
> wave is overwhelmingly the fundamental so that will be processed
> into a square wave by the Flip Flop.  If the drive to the
> multiplexer is good as you say (I can not open the JPG but it
> doesn't matter) it sounds like the local oscillator divider chain is
> correct. I can only conclude the instability reported is at the
> oscillator suggest you concentrate on that as a source of your
> problem. ..... I have run out of ideas.


> Anyway good luck and please report the solution there are a lot of
> people very interested. 73 petefmt






--
Best regards,
 Chris                            mailto:dead.fets@gmail.com