To: | LineOne <[email protected]> |
---|---|
Subject: | Re: LF: Softrock RX divider IC problem, unexpected frequency out |
From: | Andy Talbot <[email protected]> |
Date: | Sat, 27 Jan 2018 16:49:55 +0000 |
Cc: | Chris Wilson <[email protected]> |
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Looking at the schematic, I see a 74AC74 divider is used which works at over 100MHz clock frequency. You are hitting its edge triggered clock inputs with low frequency waveform (461kHz) with a slow and indeterminate rise time caused by crude semi-linear amplification plus clipping. It really is no wonder the system is not driving the divider properly. That sluggish edge has to hit the D input on both flip-flops and cause them to toggle together. I'm surprised it even appears to work at HF where the design originated.
That design with no proper logic level squarer is just asking for trouble and I'd be surprised if you ever get it to work properly. It might, perhaps, if the divider were changed to a slower 74HC74 device, but that's a bit speculative; it may be just as bad. I would suggest you stop fiddling about with component values, trying to frig an unsuitable design. You MUST feed
a proper shaped logic level to such high speed divider chips. There really is no getting round that fact. They won't work properly otherwise - just look at the specifications for AC series logic. You can keep the simple single transistor buffer, but use its output to feed the input of a shaping gate. A Schmitt like a 74HC14 (a package that has 6 suitable gates) ought to do you nicely. Bias the input mid way between its two threshold voltage - these are different for HC and HCT family devices, so consult the data sheet. AC couple your RF to the mid-biassed input and connect output to the divider.
Look at the gate output on a scope and you'll have a beautiful square wave width lovely vertical edges and perfect quadrature generation however low a drive signal you put in. Andy G4JNT On 27 January 2018 at 16:13, Chris Wilson <[email protected]> wrote:
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