On 09/01/18 10:53, N1BUG wrote:
> Thanks Andy.
> 
> I need more time to get my head around that equation. I'm still struggling 
> with 
> a near vertical learning curve on all of this. I never worked with ferrite 
> (except in RFI suppression) until very recently. To start with I don't know 
> what 
> figure to use for N turns on this 16:1 transformer with 4 x 10 turn windings. 
> There must be beginner level articles somewhere that walk one through this 
> stuff, but I haven't yet found them.
> 
> For that matter I'm not sure how to calculate Vrms on something that isn't a 
> sine wave.
> 
> All I can say at the moment is the core is a EPCOS / TDK B64290L674X830
> 
> N30 material with a ui of 4300, 36 x 23 x 15 mm.
> 
> I'm still interested in understanding the issues with this PA as a learning 
> exercise but am preparing to move on to something else for on air use.
> 
> Paul N1BUG
> 

All,

I've been, sort of, following this as I have a similar problem with the
amp at <http://www.qrp-labs.com/ultimate3/u3mods/lfamp.html> I have not
used the 2n4 cap to ground on the gate (yet) but I have added a series
resistor of 15R to the gate prior to the DC blocking cap (or should I
have put it after the DC blocking?)

My observations:

With out the 15R it was very fussy and would go into, what I presume,
was oscillation - the voltage trace on my scope match was 'fuzzy' -
looked like AM? with almost no provocations ... however lowering the
supply voltage cured this.

I have just re-worked the matching unit at the aerial and now have an
almost perfect 50R j0 match. so I know this is not a reactive issue (I
think - however the scope-match is at the shack end on a random length
of RG58 - so ...)

I played last evening and:

It still oscillated if I run it at 13.8V and drive of around 250mW (U3s
3 BS170s at 5V), drop the voltage to about 11V and all is well.

Increase the drive to about 800-900mW (U3s 3 BC170s at 13.8V nominal)
and I can wind the supply up to a little over 12V before it goes wild.
The bias is set to give about 75mA at idle.

If I reduce the bias & therefore idle current then the oscillation is
earlier & easier to provoke, if I go much over about 150mA the FET takes
off in thermal runaway with the current going skyward with no change in
bias setting - so a little under 100mA it is.

I think I have two avenues, put in the feedback as mentioned from Drain
to Gate (300R-ish & DC blocking) or make a driver stage to make sure the
FETs switch harder.

Now the AMP is supposed to be linear so the second option is not the
correct, unless I am operating in class >C

Not an answer but some data points from a simple single FET MF amp

ALl the best

Nick
M0HGU



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