Thanks Andy. These MC155170 are hard to find these days, but I have a
couple of PMB2306 chips from scrapped wireless phones waiting for a new
life. One of them has already made it into a 70 MHz synthesizer... and
on a 'nice' combination of the divider and multiplier value, as you
mentioned, the phase noise may be low enough to clock an SDR with it
(even though exactly that's what G4HUP does *not* recommend in his article).
Or maybe a 66.6666 MHz stock oscillator can be turned into a VCXO simply
by varying its supply voltage (a tiny bit).. may be worth trying.
Cheers,
Wolf .
Am 06.12.2015 um 11:46 schrieb Andy Talbot:
I did it with a simple PLL
VCO running at 66.6...MHz divided by 30. 10MHz reference input divided by 3,
Phase comparator running at 333.333...kHz
I used a superannuated obsolete MC145170 chip, but there are a
plethora of modern PLL chips out now that will do it for you.
Several types even have internal VCOs so you can have a one chip
solution (plus the programmer, of course)
Andy G4JNT
On 6 December 2015 at 10:33, Wolfgang Büscher <[email protected]> wrote:
Greetings all,
After trying a couple of modifications to my SDR-IQ, I found the following
site ..
http://g4hup.com/SDRlock.html
.. which describes how to lock the 66.6667 MHz 'ADC clock' in the SDR-IQ to
an external 10 MHz reference.
Does anyone here have own experiences with this, or a similar circuit ?
Dividing the 10 MHz reference by three, and subtracting that from 10 MHz
multiplied by 7 sounds intriguing, but a multi-pole crystal ladder filter to
'clean up' the resulting 66.6666666 MHz signal is easier said than done
(..lacking such crystals in the junk box).
73,
Wolf DL4YHF .
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