To: | [email protected] |
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Subject: | Re: LF: what causes this on wspr |
From: | Andy Talbot <[email protected]> |
Date: | Wed, 1 Jul 2015 19:58:21 +0100 |
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Its more than just PLL settling time. That could be controlled by suitable choice of loop bandwidth. At least I think it is. It could be part of the PLL's own internal VCO calibration when it is reprogrammed. First discovered this using the LMX2541 to generate WSJT modes on beacons. But found a suitable work around on that chip. Designers of the U3 with its Si5xxxx family device haven't even acknowledged the problem , don't have teh test equipment to measure it, won't take advice, and teh chip is poorly documented anyway - unlike TI's products. See next months RadCom (August issue) where I discuss in a lot more depth the problems using Fract-N synths with internal VCOs when generating MFSK modes and why these occur. Andy On 1 July 2015 at 19:48, Graham <[email protected]> wrote:
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