Hi Andy
Why not simply OR the xx% duty cycle with the PN sequence and suppress
repeated TX sequences in a row? This should create something code
compact and simple that lets you sleep at night that can be pretty easy
to make appear 'random.' Also add the ability to your code to allow the
user to select their own seed word.
A 256bit LFSR sequence run over a WSPR period would take along time for
someone to figure out a pattern. Larger sequences would only take abit
more effort to code and if your writing in C no real effort at all.
I think Joe K1JT lost some sleep over this as well. You should drop him
a line as he is most helpful about such dialog.
I ran into similar aesthetic issues simulating fire light with LFSRs
years ago and found that many of them operating in tangent with each
other produced very layered and real appearing effects.
Another solution I have tried is an ADC or clipper/clamp circuit on an
input of the MCU and an inductorless Chua's circuit driving it... Period
three implies Chaos.
http://www.cpdee.ufmg.br/~MACSIN/services/papers/toraguel.pdf
gl es 73
Scott
VE7TIL
Andy Talbot wrote:
Scott:
Its precisely that an LFSR does not give what is needed that made me
start thinking along these lines. For one thing, LFSRs are only
random if considered over the whole repeat length, viz 2 ^ N - 1 bit
for a maximal length sequence. They will have one single run of
exactly N ones, and N-1 zeroes, and a predicatable numbers of runs of
fewer successive equal bits. It is a well established annoyance with
these that short register lengths cannot be used to generate
half-decent pseudo randomness
What I was idly speculating on was a straightforward way of generating
a semi-random sequence with deliberately limited continuous runs of
ones or zeroes. By forcing this aspect, the sequence cannot possibly
be random. A ideal sequence would probably have very little
statistical randomness at all. But it sems to have turned out to be
not at all straightforward.
Eg 33% duty cycle with no randomisation
001001001001001001001001001001
A true PN sequence at 33% could be like
010000111100100000001100101000
which has an excessively long sequence of ones for WSPR Tx purposes
A more optimised pattern might be
001010100001010100100010001010
Apart from one bit, this one is actually a smaller pattern repeated.
Which all comes down to the idea that its easiest to just generate (by
inspection !) a set of precomputed tables - but that just feels like
cheating and I feel dissatisfied with it :-)
Andy
www.g4jnt.com
2009/2/21 Scott Tilley <[email protected]>:
Hi Andy
Try a 'Linear Feedback Shift Register', Google it...
Very simple to implement in a MCU and can be scaled to any size you like. I
wrote some code to do this in PIC assembly years ago that was only a few
lines long for a 256bit sequence...
Best of all you can predict the outcome and choose a sequence that meets
your needs given a unique seed word....
Better yet it offers a means of identification over a long term integration
:-)
73 Scott
VE7TIL
Andy Talbot wrote:
...but if any mathematicians, number theorists or cryptographers
should be reading this...
I've just got a WSPR generating routine running on a PIC / AD9852 /
GPS combination, but I'm looking for a half-decent way of generating a
pseudo random Tx/Rx sequence with defined duty cycle that does not
give the long(ish) consecutive runs of 0's or 1's that MUST ALWAYS
occasionally be seen in a truly random sequence.
In other words, the sequence needs to be bandpass filtered.
Before I cop-out and just use a pre-generated set of lookup tables,
take a look at http://www.g4jnt.com/WSPR_PN_Sequence.pdf
for a fuller description of the mind-bender
Andy G4JNT
www.g4jnt.com
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