The filtering requirements are less onerous if the
dithering frequency components are maximized, e.g. by
a DDA algorithm. In Johan's example, add 442 to a
variable each main PWM cycle. If the result is less
than 1024, send 705 to the PWM. Otherwise, send 706
and subtract 1024 from the variable. This results
in a sequence of 705, 705, 706, 705, 706, 705, etc.
----- Original Message -----
From: "Johan Bodin" <[email protected]>
To: <[email protected]>
Sent: Thursday, May 13, 2004 4:42 PM
Subject: LF: Re: VDC source with microvolt resolution
Jim mentioned using a DAC to interpolate between the PWM steps.
The interpolation can also be done by "PWMing the PWM" between
two adjacent PWM steps (sort of "controlled dithering" :-).
1024 main PWM cycles = 1 sub-PWM cycle.
For example, if the MSWord = 705 and the LSWord = 442 (10-bit words)
then the main PWM should be set to 706 for 442 of the PWM cycles and
to 705 for the remaining 1024-442=582 cycles.
I recall we discussed this approach for VCXO control some time ago.
The downside is that the output signal will contain frequency components
as low as the main PWM frequency divided by the sub-PWM resolution
so you'll need a very "slow" lowpass filter to get rid of the ripple.
A DC accurate multi-pole filter with good (perhaps chopper stabilised)
op-amps should do the trick.