It rests to see if the AT90S8535 (you know that, do you ? :-) allows this
"change over the nose" of the PWM limits fast enough to be effective.
I can't see that as a problem. Timer1 overflow flag works in PWM mode too
so it is possible to write an interrupt routine that is synchronized to the PWM
cycle. Every time the ISR is fired, it reads the 20-bit value from a global and
updates the 10-bit PWM control register with either N or N+1, according to
the "sub-PWM" algorithm.
I like Stewart's idea of maximizing the dither frequency by spreading the N+1
corrections all over the main PWM cycles but I don't know enough math for
optimizing it. What if the value of the 10 LSBits is 1 for example? It cannot
be spread out and there will be some some Fpwm/1024 frequency component
(although very small).
Given that a correction does not happen more often than once every 30
seconds, also the lowpass filtering of the control voltage should not be a great
Assuming 8MHz clock on the '8535 (Yes, I know it :-), main PWM frequency
is 3910 Hz max in 10-bit mode. Adding a 10-bit sub-PWM brings the lowest
frequency component down to 3910/1024 = 3.8 Hz. A 3:rd order LPF with
0.3 Hz cut-off, or so, should be about 60 dB down at 4 Hz and still have a
reasonably fast response. With more filter poles you should be able to put the
cutoff "knee" closer to 3.8 Hz and get faster response without sacrificing
"sub-PWM" ripple rejection. Maybe a Bessel response is preferable to
avoid overshoot although Bessel has a very "lazy" roll-off compared to
Butterworth et. al.