Re: LF: G0MRF/SM6LKM DDS VFO and Jason

["John Andrews" <w1tag@charter.net>]

Andy,

> That's neat! But I make it 0.0083333 Hz resolution, (still OK nice value
> though) and can't be locked to a 1PPS signal.  Better still, use it with
an
> AD9851 chip using the x6 PLL multiplier for 50mHz steps.
Good thought. My only real goal in this case was to have the divisor remain
an integer down to 10 mHz intervals, as I was using an 8-bit controller with
display and keypad. For the moment, calibration against a well-calibrated
ARGO screen has been sufficient, but I would obviously need to tune the DDS
to some "magic" frequency to use more accurate methods.

John Andrews, W1TAG