Dear Klaus,

Like John G4CNN, I have been thinking about your CRT DDS scheme..

Firstly, a rather long winded recap on DDS/NCO operation:

Assuming a simple DDS with an 8 bit latch and an 8192 Hz clock.

With the smallest possible increment (one), the counter goes through 256
steps before wrapping around the unit circle. At each step the Latch reading
is used to look up a value in the ROM. The ROM table contains one full cycle
of a Sine Wave.

With an Increment of one, the output goes through a full Sinewave every 256
clock pulses and thus (in our example) generates 32 Hz.

The maximum possible output frequency is where only two steps occur each
unit circle, thus the Max frequency is half the clock frequency (4096Hz).
This occurs at an increment of 128.

Intermediate steps thus give an output range from 32Hz to 4096Hz, with 128
steps
every 32Hz. (The frequency step size is given by dividing the Clock
frequency by the max latch count).

In the special case where the increment value is a power of two (1,2,4,8,16,
etc),
the DDS steps land exactly on the minima and maxima of the wave (eg
includes counts of 0, 64, 128, 193, 256). At all other frequencies the
samples
miss the min/max/zero and thus the output contains some jitter
(unless considerable "Q" is available to act as a Flywheel).

The above is (I think) the Address Quantitisation which Klaus mentions.

I am guessing that Klaus has discovered a system where the effective
Latch size is changing for each different frequency, thus ensuring that
the generated wave always has samples at the peaks and troughs.

Is this correct so far Klaus ???

But then perhaps I am on the wrong track completely.

............................. Zim