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References: [ +subject:/^(?:^\s*(re|sv|fwd|fw)[\[\]\d]*[:>-]+\s*)*LF\:\s+Re\:\s+Class\s+D\s+current\s+spikes\s*$/: 13 ]

Total 13 documents matching your query.

1. LF: Re: Class D current spikes (score: 1)
Author: Rik Strobbe <[email protected]>
Date: Sun, 24 Feb 2019 12:38:57 +0000
Hello Eric, I had a similar problem: at "key up" one of the driver outputs will remain low and the other high. As a result the gate of one of the power MOSFETs is kept high for a time much longer tha
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00200.html (11,026 bytes)

2. LF: Re: Class D current spikes (score: 1)
Author: Rik Strobbe <[email protected]>
Date: Sun, 24 Feb 2019 13:21:41 +0000
Addendum: 3 microseconds is for 472kHz, for a 136kHz PA it should be 10 microseconds. 73, Rik ON7YD - OR7T Hello Eric, I had a similar problem: at "key up" one of the driver outputs will remain low a
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00201.html (12,451 bytes)

3. Re: LF: Re: Class D current spikes (score: 1)
Author: Andy Talbot <[email protected]>
Date: Sun, 24 Feb 2019 13:29:35 +0000
Why not AC couple your gates.  That removes all possibility of latching 100nF in series, reverse biassed diode to ground shunted by 10k or so for DC restoration Or transformer couple Andy www.g4jnt.c
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00202.html (15,297 bytes)

4. Re: LF: Re: Class D current spikes (score: 1)
Author: Eric NO3M <[email protected]>
Date: Sun, 24 Feb 2019 08:35:38 -0500
Rik Thanks for the reply.  This particular build is current mode (choke off center tap)... so I guess I'm dealing with voltage spikes.  I didn't notice voltage spikes while monitoring the envelopes w
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00203.html (10,356 bytes)

5. Re: LF: Re: Class D current spikes (score: 1)
Author: Eric NO3M <[email protected]>
Date: Sun, 24 Feb 2019 08:42:15 -0500
The driver and FET gates in mine are AC coupled (0.22u, SB560 schottky shunt, 10 ohm series, 4.7k shunt) and the problem still exists.  Apparently same thing Paul N1BUG was having problems with.  The
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00204.html (11,419 bytes)

6. Re: LF: Re: Class D current spikes (score: 1)
Author: N1BUG <[email protected]>
Date: Sun, 24 Feb 2019 09:03:52 -0500
I will be watching this discussion closely. Mine is a W1VD kilowatt deck: http://w1vd.com/137-500-KWRev3.0.pdf It has blown FETs several times. The problem always occurs at the end of the RF envelope
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00205.html (14,067 bytes)

7. Re: LF: Re: Class D current spikes (score: 1)
Author: Rik Strobbe <[email protected]>
Date: Sun, 24 Feb 2019 14:23:12 +0000
Hello Paul, Eric, Andy, AC coupling with a large C will not solve the problem. At "key up" one of the driver outputs will remain high thus the gate of theFET connected to that output will remain high
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00206.html (12,174 bytes)

8. Re: LF: Re: Class D current spikes (score: 1)
Author: Andy Talbot <[email protected]>
Date: Sun, 24 Feb 2019 14:41:57 +0000
For on-off keying of a switch mode PA you really should be using supply line control.  Switching the drive then trying to reduce rise /fall times for keyclick elimination by controlling drive amplitu
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00207.html (15,335 bytes)

9. Re: LF: Re: Class D current spikes (score: 1)
Author: Eric NO3M <[email protected]>
Date: Sun, 24 Feb 2019 13:04:52 -0500
Andy This recommendation is all well and good, but seems applicable to only CW where either the operator is manually keying or using computer controlled keying with a constant carrier input. With dig
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00210.html (14,696 bytes)

10. Re: LF: Re: Class D current spikes (score: 1)
Author: Andy Talbot <[email protected]>
Date: Sun, 24 Feb 2019 18:20:02 +0000
IN that case some sort of protection needs to be incorporated - and few have come up with really properly designed and foolproof circuitry. I use the technique adopted in the hold Decca transmitters,
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00211.html (17,630 bytes)

11. Re: LF: Re: Class D current spikes (score: 1)
Author: "[email protected]" <[email protected]>
Date: Sun, 24 Feb 2019 15:26:31 -0500
Eric One or two FETs per phase? Jay W1VD -- Original Message -- From: Eric NO3M <[email protected]> Reply-To: <[email protected]> To: <[email protected]> Sent: 2/24/2019 1:04:52 PM
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00212.html (15,386 bytes)

12. Re: LF: Re: Class D current spikes (score: 1)
Author: Eric NO3M <[email protected]>
Date: Sun, 24 Feb 2019 16:00:58 -0500
Jay Just one FET (59N25) on each side. On 2/24/19 3:26 PM, [email protected] wrote: Eric   One or two FETs per phase?   Jay W1VD    
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00213.html (11,300 bytes)

13. Re: LF: Re: Class D current spikes (score: 1)
Author: <[email protected]>
Date: Mon, 25 Feb 2019 09:02:16 +0000 (UTC)
Try using a synchronous keying circuit, only uses a few ics and is reliable. I have used it on a modified Decca 5501 on 136 and a similar tx on 475 with no blown fets even to a short circuit, guard c
/rsgb_lf_group-archives/html/rsgb_lf_group/2019-02/msg00214.html (13,182 bytes)


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