Re: LF: W1VD amp help - more waveforms

[N1BUG <paul@n1bug.com>]

Chris,

I think it was after looking at your driver board photos that I
decided to order these particular caps. They look exactly like
yours. ;-)

I haven't tried the bypass caps yet. Given we're now testing without
generating any RF (no drain voltage on the FETs) I'm a bit dubious
but I will try them. It's four caps, right? Pin 14 of the 74F74 to
ground, pins 9, 3, and 6 of the IR2210 to ground.

The other day Jay asked about power to the IR2110 and trace
thickness... which might affect drive to the FETs but probably not
the timing issue we're now chasing. However, for sake of
completeness in this thread it's a 25 amp supply!!! through 3 feet
of #18 wire to the board. The weakest link is about 3 inches of #22
wire from the board +12V input terminal to pins 3 and 6 of the
IR2110. Anticipating a possible question... no it's not the same
supply I'm using for the FET drains, just a spare bench supply that
was conveniently located for testing.

Paul


On 04/11/2018 07:40 AM, Chris Wilson wrote:
> 
> 
> Hello  Paul,  effectively  the  same as I am using, so I think you can
> safely  discount those. Have you tried de-coupling caps yet, especially
> on the driver IC?  I think the hump on the gate waveform is the driver
> overcoming the gate capacitance of the FET's.
> 
> Wednesday, April 11, 2018, 12:30:38 PM, you wrote:
> 
>> Jay,
> 
>> The caps I used are polyester. Here's the datasheet:
> 
>> https://www.mouser.com/datasheet/2/212/KEM_F3101_R82-1103738.pdf
> 
>> It mentions timing applications, but I am no capacitor expert!
>> Comments appreciated. Mine are 5% tolerance marked 1nJ100.
> 
>> I always measure resistors because I don't trust my eyes. The ones
>> used here measured about 14.98k on my Fluke DMM.
> 
>> My proto board construction technique uses 'rows' of solder which
>> undoubtedly results in higher than usual stray C. However I would
>> expect it to be a few pf, not something that would throw the circuit
>> off this much.
> 
>> Paul