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LF: RE: Todmorden receiver

To: <[email protected]>
Subject: LF: RE: Todmorden receiver
From: <[email protected]>
Date: Sat, 25 Nov 2017 18:30:30 -0500
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Hello Paul,

I'm guessing that you've considered all of the below but just in case:

Erratic power supply startup related to the comparatively high source 
resistance of long wires and associated connectors, can often be eliminated by:
a) Slower soft-start (larger valued soft-start capacitor)
b) Within limits, a bigger input capacitor at the DC-DC converter input 
c) If the DC-DC converter soft-start is not accessible (at the PWM IC's soft 
start pin or equivalent), in some cases introducing an RC time constant at the 
PWM regulator integrated circuit's Vref pin will work, but see (d) below
d) Regarding (c) above, if the PWM regulator IC's Vref pin controls 
housekeeping supplies inside of the IC, the technique of ramping the PWM 
regulator IC's Vref cannot generally be used, but still may merit cautious 
investigation: if cautiously evaluated it can solve the problem for a given 
revision level of the IC. I mention this approach only because it sometimes is 
the only available option, and even if the PWM IC's Vref pin controls 
housekeeping supplies inside of the IC, margin testing the approach at various 
loads, input voltages, source resistances and in cold/hot air often provides a 
reliable fix for a given revision level of the IC.      
(e) If you have plenty of source voltage overhead, and the PWM IC's 
undervoltage lockout (UVLO) node is accessible, changing a resistor at the UVLO 
node (raising V_UVLO) can (by itself or in combination with one or more of the 
above) fix the problem.   

Considerably reducing DC-DC converter output filter capacitance and/or load 
current can almost always solve the problem of erratic power supply startup 
related to high source resistance, but is almost never an option given 
stability, noise and load current constraints. I mention this just to 
illustrate that the high-source-resistance erratic power-supply startup problem 
usually involves C_out plus R_load inrush current (occurring after UVLO enables 
the power switch) passing through C_in ESR, thereby sagging V_in below V_UVLO, 
resulting in (small or large) oscillation wherein V_in_avg < V_UVLO.



-----Original Message-----
From: [email protected] 
[mailto:[email protected]] On Behalf Of Paul Nicholson
Sent: Saturday, November 25, 2017 4:21 PM
To: [email protected]
Subject: VLF: Todmorden receiver

It looks like I'm on the finishing straight now with this new E-field receiver. 
 Started in March 2013 and now it's
almost working!    It took about a year to get the old rx to
work properly and it's been out in the field since September 2003, looking 
distinctly shabby now after 14 years of Pennine weather and attacks by cows and 
sheep - but it's still working.

It's taken 3.5 years to improve on it.  How can it take so long to build an 
audio amplifier?

The answer would make a long and perhaps interesting article if I had time to 
write it.  It would mostly be a list of things
that didn't work and why.   Much time was spent trying to do
away with the isolating transformers but eventually I had to admit defeat.  
Transformers bring with them a lot of problems but they are hard to beat.  
Things that work fine on paper, and even test fine on the bench, just don't 
hack it when deployed and carrying real signals.  I wanted to cover ULF, down 
to 1Hz, but that turned out to be very problematic indeed. Digitising near the 
antenna would solve a lot of these problems but the technology to do that 
reliably with sufficient quality isn't quite there yet.

Right now the new rx is layed out on the bench, complete with 150m of cat5, 
running an end-to-end system test. System noise measures 14nV/m equivalent 
E-field and Spice is predicting 18nV/m.  The output noise of the rx is only 9dB 
above the M-Audio 192 sound card noise floor at 8kHz.

I'm making good use of vtcat ++ to send the full 192k/sec VLF raw signal from 
one of the loops into the office to use as a test input to the rx on the bench, 
so now I'm listening to VLF that's been received twice!

Response is good at 137kHz too, I've no means to measure the system noise up 
there but Spice is showing about 10nV/m.  I just need to work out a way to 
T-off the 137 at the bottom of the
cat5 without complicating the VLF response and compromising the
isolation.   There's still a problem with the DC-DC converter
in the rx, it doesn't always start up when power is applied, something to do 
with the series resistance of the cat5.
The calibration port works real well and a re-build of the antenna has cured 
some microphonics.  The antenna models accurately using LCnetgen, capacitance 
measures within 2pF of the model which means I can trust the model's effective 

Next on the agenda is a re-build of the H-field rx.  That should be a lot 
easier, it's just some small changes to improve the frequency response, a new 
line driver, better isolation, and reduction of cross-talk between the two 

When it's all working, the online steerable spectrogram will have a 360 degree 
compass and a few dB more sensitivity - it will be interesting to look at 
VO1NA's signal then!

Paul Nicholson

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