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Re: LF: Image-Cancelling Exciter

To: [email protected]
Subject: Re: LF: Image-Cancelling Exciter
From: Wolf DL4YHF <[email protected]>
Date: Mon, 17 Jan 2005 20:49:01 +0100
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Hi Rik and John,

Another problem with the 4017 "Johnson" counter is, the output timing is not very precise because it is an asynchronous counter. To divide by 4, one of the 4017's outputs (Q4) must be connected to the RESET input to reset the counter if the 5th output is set. The time required to reset the counter, no matter how short, will be missing in one of the 4 "wanted" output pulses (Q0 to be precise). So the length of the 4 output pulses will differ by some XX nanoseconds. A synchronous counter (or divider) where all clock inputs are connected in parallel will perform better, there will be no difference in the propagation delays for all 4 outputs. Furthermore, the 74HC107 provides the inverter for the 74HC4066 for free. I tried to measure the delay between inverting and non-inverting output from one flipflop, it was below 2 ns (no accurate measurement possible with a 60MHz-scope).

Regards,
Wolf DL4YHF .


John Andrews schrieb:

Rik,

if you want to use 4000 series logic in fast speed applciactions it can be
used at 15V. This will increase the speed by a factor 3..4 compared to 5V.

Agreed. But I would not have been able to use the 74HC4066 switch, and I
wanted to stick with that.

John A.








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