What is the output configuration from the Iout pin(s), 20/21, on the AD9850
to any anti alias filter? Secondly, what is the value of the Rset resistor
on pin 12 - this sets the full scale current from the internal D/A converter
- a value of 3k9 sets 10mA full scale? With this current, single ended,
into an impedance of 100 ohms (recommended on the data sheet) an output
voltage of 353mV RMS should result. In the data sheet, the anti alias
filter shown is designed for a Z0 of 200 ohms, and sits between 200 ohms
resistors each end - giving the total 100 ohms load for one single Iout port
the DDS.
However, you appear to quote a 50 ohms load so 10mA full scale into this
will result in only 177mV RMS which is roughly in the region of the figures
you have measured. Now, your filter - particularly if is is an elliptic
type with a sharp cut off - will have some quite wild impedance fluctuations
in its passband and will likely result in the variations in level seen.
Furthermore, there is a sin(x)/x roll off attenuating the top end of the
frequency rsponse, although this only gives 1.6dB signal reduction at 40MHz
My own preference, these days, for terminating the AD9850/51/52 family is to
use a balanced ferrite transformer, making use of both Iout pins in
push-pull to gain another 3dB, with 50 ohm operation. I usually adopt a
trifilar wound transformer with a turns ratio of (1+1):1 with a true 50 ohm
termination. The transformed impedance is therefore 200 ohms connected
BETWEEN the two Iout pins, and gives 100 ohms each side with the centre tap
connected to ground. Now, the output level can be measured accurately with
50 ohm test equipment, without the encumbrance of the anti-alias filter.
The filter can then be set up separately between 50 ohms ports and conencted
separately.
Using this arrangement, a raw output level before the filter of 7dBm (in 50
ohms)is easily achievable - the Rset resistor can be reduced (check the data
sheet for the limitiations here) for a higher Iout, and powers potentially
in excess of 10dBm. With the 5V AD9850/51 devices, the turns ratio could
even be made a bit higher for an increased Rload, like (1.2+1.2):1 for even
more output.
Andy G4JNT
-----Original Message-----
From: G4WGT - Gary [mailto:[email protected]]
Sent: 2004 February 05 18:39
To: [email protected]
Subject: LF: RE: G0MRF 300w Tx & DDS VFO
Hi Alan & LF,
The frequency calibration of my DDS VFO is so good (with a little hit & miss
twiddling)that it is zero beat with BBC Radio 4 on 198 Khz radio
transmission & the freq stability is every bit as good, during hours of
testing with 198 Khz as a reference I cannot detect any variation.
The problem as I have specified in my e-mails is the low output. Last night
I checked back to the DDS IC & there are no substantial losses in the signal
path, even the insertion loss of the LPF is negligable. Here are the actual
levels into 50 ohm load at the output of the DDS VFO.
137 & 274 Khz - 22mV
1.0 Mhz - 50mV
2.0 Mhz - 60mV
5.0 Mhz - 80mV
10.0 Mhz - 150mV
15.0 Mhz - 250mV
20.0 Mhz - 250mV
25.0 Mhz - 150mV
30.0 Mhz - 75mV
35.0 Mhz - 65mV
40.0 Mhz - 50mV
I am also sending this info to the organiser of the offer/project from the
G-QRP Club asking for his help, advice or a further contact point.
By the way, the DDS chip is a Analog Devices AD9850 w/ 120 MHz Clock
73
Gary - G4WGT
-----Original Message-----
From: [email protected]
[mailto:[email protected]]On Behalf Of Alan Melia
Sent: 03 February 2004 21:53
To: [email protected]
Subject: LF: Re: RE: Re: Re: G0MRF 300w Tx & DDS VFO
Yes Ok Gary, I guessed it was so. I just wondered whther you had a "tight"
filter. The signal out of the chip (do be carefull here) should be a logic
level ..i.e. 5v p-p I would have thought (??)
Cheers de Alan G3NYK
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