[email protected] wrote:
There does not have to be a frequency error at all for a phase comparator to
output a correction voltage...only for the oscillator being stabilized to
have a _tendency_ to drift away from the desired frequency, which is
inevitable. Hence, once lock has been achieved, a more-or-less constant
phase difference is maintained by the loop. This is not frequency error.
I am not quite convinced yet... :-)
Time is the difference between frequency and phase, as in Alan's analysis. A
_frequency_ difference between two signals means the _phase_ relationship is
changing continuously in the same direction over the course of time. If f1 >
f2, the phase of f1 is constantly advancing relative relative to that of f2,
for just as long as the frequency difference is allowed to exist. This is
the condition when lock has not been achieved.
Allow me to quote from the book "Phase Locked Loops, Principle and
Practice",
McGraw Hill 1996, by P.V. Brennan University College, London.
Page 22: "...As far as the control loop is concerned, it should be noted
that
frequency dividers act equally as phase dividers, so that a factor of
1/N must be
allowed for in the loop equations".
When a PLL achieves lock, phase of the controlled oscillator is NOT allowed to
move continuously in either direction. There may be short-term variations
around the center, but no continuing trend (thus, phase lock). Without
continuous phase change in a given direction, there is no frequency error
relative to the reference. The remaining short term variations around the
desired phase relationship are simply that: phase noise, or jitter.
Now from the same book, page 128, where the author describes a PLL that
includes a
divider-by-1000 between the VCO and the phase comparator:
"...the implementation of figure 8.6 has a resolution of 0.35 degrees.
Although
this may sound impressive, it should be realized that the resolution
referred to
the VCO is worsened by a factor of N, to 350 degrees for example, with a
divider
ratio of 1000."
73
Andre' N4ICK
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