Hi Markus, yes.
its all done in a simple 8 bit PIC using a crafty idea suggested by
G3PLX back around the year 1997, but which can now make use of the
better A/D Dconverters in the later chips
(Apologies to readers of last month's and the latest RadCom - you may
get a sense of Deja-Vue with what follows here )
The Rx process is: digitise a Band pass Filtered signal centred on
1kHz at a sampling rate of exactly 4kHz. 10bit A/D in the PIC. Take
groups of four successive samples , call these S1, S2, S3 and S4.
Calculate using simple signed-integer maths I = S1+S2-S3-S4 and Q =
S1-S2-S3-S4. The four samples at 4kHz are equivalent to the segments
making up a pair of quadrature 1kHz square waves. The effect is to
multiply the input waveform by a complex local oscillator, which being
a square wave only requires multiply by +1 or -1. Output the two
resulting 12 bit numbers on the RS422 interface to a PC
Bandpass filtering removes frequencies below 750Hz and above 1250Hz
that would otherwise alias into the wanted area.
Theoretically, even with a significant A/D DC offset that would be
cancelled out in the sums. I think the value I see amounts to no
more than one bit in 12 of bias, but with low levels of RF in that can
be seen on the FFT in 0.122Hz bins. As soon as the input signal
approaches 20% or more of maximum amplitude the spike is hidden.
You have, however, just this very minute, made me think of something
though....
The output data is sent repeating at 1kHz so there is something in the
box with real 1kHz components. Which would explain why the spike is
more noticeable now I added 1kHz gain than when RF gain was in place.
THAT may be it... Investigation needed
Andy G4JNT
On 10 December 2015 at 10:52, Markus Vester <[email protected]> wrote:
> Hi Andy,
>
> presumably the digital 1 kHz-to-baseband conversion is done in an FPGA or
> DSP in realtime. The associated periodic processing activity or register
> content could lead to a 1 kHz component radiated by the FPGA itself or it's
> DC power lines. This could then leak into the analog audio input to the ADC.
> Try sniffing around the FPGA with a capacitive or inductive probe.
>
> Downconverting from a soundcard on a PC in software usually does not suffer
> from such coherent leakage, as there are variable delays due to buffering
> and multitasking which effectively remove the periodicity in the CPU
> activity.
>
> Best 73,
> Markus
>
> -----Ursprüngliche Mitteilung-----
> Von: Andy Talbot <[email protected]>
> An: rsgb_lf_group <[email protected]>
> Verschickt: Do, 10 Dez 2015 11:23 am
> Betreff: Re: LF: LF EbNaut test from JN80 on 137370
>
> ...
>
> My LF receiver appears to give a small DC spike in the centre of the
> spectrum , which since it is taking input at 1kHz and multiplying in
> firmware with I/Q square waves is a bit odd. That DC term wasn't
> noticeable when I had the RF amplifier previously (the one that popped
> with strong signals) but now gain has been moved to 1kHz IF, the line
> can be seen. Perhaps an RF amplifier is necessary, but one that can
> safely be overloaded
> ...
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