In a message dated 1/20/01 4:27:03 PM Eastern Standard Time,
[email protected] writes:
<< For simplicity's sake, let's assume that we have a phase comparator that
needs a 1 Hz difference between its two inputs before it creates a DC
correction signal large enough to control the VCO (not a very good phase
comparator, assuredly, but just for demonstration purposes). >>
Ah, but that's the point. It would be an extraordinarily bad phase
comparator if it didn't begin to respond until there was a 360 degree/second
error. A PLL using such a comparator could probably never achieve lock. At
best, it would wander loosely around the hoped-for frequency.
There does not have to be a frequency error at all for a phase comparator to
output a correction voltage...only for the oscillator being stabilized to
have a _tendency_ to drift away from the desired frequency, which is
inevitable. Hence, once lock has been achieved, a more-or-less constant
phase difference is maintained by the loop. This is not frequency error.
Time is the difference between frequency and phase, as in Alan's analysis. A
_frequency_ difference between two signals means the _phase_ relationship is
changing continuously in the same direction over the course of time. If f1 >
f2, the phase of f1 is constantly advancing relative relative to that of f2,
for just as long as the frequency difference is allowed to exist. This is
the condition when lock has not been achieved.
When a PLL achieves lock, phase of the controlled oscillator is NOT allowed
to move continuously in either direction. There may be short-term variations
around the center, but no continuing trend (thus, phase lock). Without
continuous phase change in a given direction, there is no frequency error
relative to the reference. The remaining short term variations around the
desired phase relationship are simply that: phase noise, or jitter.
I hope this helps clarify the distinction.
73,
John
|
