Return to KLUBNL.PL main page

rsgb_lf_group
[Top] [All Lists]

Re: LF: Re: Digital Sine Generators

To: [email protected]
Subject: Re: LF: Re: Digital Sine Generators
From: "Klaus von der Heide" <[email protected]>
Date: Thu, 24 Jan 2002 11:16:44 +0100
In-reply-to: <003701c1a49f$a026feb0$0886a4cb@CO3043446A>
Reply-to: [email protected]
Sender: <[email protected]>


Hello all,

Zim wrote:

Thank you for your good humour and patience in answering my dumb questions.
It's embarrassing for me to show my ignorance in public, but it's worth it
if
I learn something useful.

The mathematician would say: The only dumb question is the empty question.

For a long time now I've been trying to understand the practical trade-offs
in DDS design.

So let's see if I have this DDS Distortion thing right ...........

Memory Quantisation:
----------------------

If all of the bits in a DDS latch are used to drive the Sine ROM, then there
is NO problem with memory quantisation.

If the Latch has many bits (e.g. to get fine frequency steps) then the ROM
will have to be excessively large. If only the higher order bits are used to
drive the ROM, then the wave generated will have a degree of roughness.

Yes, this roughness is additional to the inevitable value quantization of the memory words which you mention further below. The effect of address quantization often is much greater.

In the special case where the low order (unused) bits do not change (e.g.
where the matching low order Increment bits are at zero), then there is also
no quantisation error (is this correct?).

Yes and no. See above. The quantization of the memory words remains. But the effort to get this smaller by longer words is linear in complexity. That means, each further bit gives a gain of 6 dB. In contrast, the effort to get the effect of address quantization smaller is exponential. To gain 6 dB, you have to double the memory.
Question: If we use a modern DDS chip, but limit the steps used to those
which only exercise the ROM address lines, does this give us a more pure
signal ?

Yes. But that is a severe limitation. And modern DDS chips often have implemented extra hardware for dithering which smoothes out the effect over ALL frequencies. You cannot switch off that.

In practical DDS design, there are various methods to increase the
resolution without increasing the ROM size. One method is to interpolate the
"missing" readings. The simplest would be to draw a straight line between
the two readings and then subdivide it into as many points as are required.

Yes, interpolation is the best way to reduce the error. But linear interpolation is not sufficient. Implementation of a Taylor approximation is easy since the derivations of sin are cos -sin -cos sin and so on. So you have all the coefficients from your sine table. But it requires an arithmetic unit.

D/A Quantisation:
-------------------

This is caused by the limit to the number of bits in each ROM location.

Yes, we mentioned that above. When the phase step is chosen such that only a few memory words are addressed periodically, the spectrum of the periodical quantization error (that's not a sine!) concentrates the power into equidistant spikes, that are mirrored at half the sampling frequency and at 0 again and so on. This also can be smoothed out by dithering. But a dither generally raises the noise level.


Now, let us review the method with the Chines Remainder Theorem:
We have no address quantization. But we have value quantization of the memory words. And additionally we have some rounding error of the arithmetic that computes the final result. That's the same if we use a Taylor-approximation. I found that the DDS with the Chinese Remainders is easier to implement and much more efficient on a DSP than a classic DDS with interpolation.


73 de Klaus, DJ5HG



<Prev in Thread] Current Thread [Next in Thread>