Hi, I thought a separate thread best for this question
U3S exciter for MF, taking the X2 frequency output @ circa 950 kHz
from the Si5351A CLK0 output pin to a level converter using a
SN74AHCT125N buffer between the si5351a and the HEF4013 flip flop,and
we are seeing something we do not understand, maybe someone can
explain?
We have an adjustable voltage regulator off the main 12V supply for the
HEF4013, next to it on my little driver board, and by chance, we found
that as we lower the voltage to the HEF4013 the drain waveforms clean
up, and just before the 4013 shuts down they are relatively good. I'll
link to scope shots.
We have the driver board grounded right by the driver IC ground points
to as near the FET source pins as the layout will allow (10 mm or so,
copper sheet strap) Before we go further we would like to know why
reducing the voltage to the 4013 improves things! We also see the gate
waveforms go negative when the FET's have power to them, without
voltage applied they are perfectly square. You can see this effect in
the screenshots. Gates are lower traces, drains upper. Thanks.
We are building a board using a CD74HCT74E flip flop in the meantime,
we suspect a 4000 series is not the best choice...
http://www.chriswilson.tv/4-point-8v-on-4013-25v-on-drains.png
http://www.chriswilson.tv/6v-on-4013-25v-on-drains.png
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Best regards,
Chris mailto:[email protected]
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