Andy,
But isn't the accuracy and stability of a cheap colour subcarrier xtal,
pulled more than 100ppm from its normal operating point, going to swamp the
values you derive from the 'nice' numbers generated with integer maths ?
Not if it is phase locked to the 5/10MHz standard.
My idea was to use a second DDS chip as divider (with fixed "nice number"
phase increment) to get a "nice number" PLL reference frequency. The VCXO
is then the only odd-ball frequency in the system.
See attached block diagram.
73
Johan SM6LKM

|