Hi Alberto, Jim mentioned using a DAC to interpolate between the PWM steps. The interpolation can also be done by "PWMing the PWM" between two adjacent PWM steps (sort of "controlled dithering" :-).
Hi Stewart, another interesting suggestion to add to the "bag of tricks" for this project ! Thanks. 73 Alberto I2PHD -- Hi Alberto, The filtering requirements are less onerous if the dithering freque
I can't see that as a problem. Timer1 overflow flag works in PWM mode too so it is possible to write an interrupt routine that is synchronized to the PWM cycle. Every time the ISR is fired, it reads
Good. You analysis shows that what remains as a concern is only the noise. Anybody knows of an op-amp (readily available) better than the OP27, as far as noise is concerned ? TNX. 73 Alberto I2PHD De
Dear Jim, thanks for your further considerations. I will have a look at those opamps. And yes, working at the uV level is a bit of challenge. I wonder if reducing the Hz/V sensitivity of the EFC with
