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Content preview: Hello Group, Planning a new single-ended Class E PA for my
activities on the Dreamers Band (8.27 kHz) two questions came up - perhaps
someone can help me: - Being interested only in on-off-keying I´m concerned
about the capacitor in parallel to the power FET which in my case on VLF
will be in the uF range. If the DC supply is on and without gate drive this
capacitor is charged to the DC supply voltage. At the first positive gate
pulse it discharges via the drain-source-path, the current being limited
only by parasitc impedances - a poorly defined condition which usually has
to be avoided. Does this mean that I have to apply drive continously and
key the DC power supply only, perhaps synchronously to the next positive drive
pulse? [...]
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Subject: LF: Class E PA
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Hello Group,
Planning a new single-ended Class E PA for my activities on the Dreamers=20
Band (8.27 kHz) two questions came up - perhaps someone can help me:
-=C2=A0 Being interested only in on-off-keying I=C2=B4m concerned about t=
he=20
capacitor in parallel to the power FET which in my case on VLF will be=20
in the uF range. If the DC supply is on and without gate drive this=20
capacitor is charged to the DC supply voltage. At the first positive=20
gate pulse it discharges via the drain-source-path, the current being=20
limited only by parasitc impedances - a poorly defined condition which=20
usually has to be avoided. Does this mean that I have to apply drive=20
continously and key the DC power supply only, perhaps synchronously to=20
the next positive drive pulse?
- Is there any rule of thumb for the inductance of the rf choke in the=20
drain-power supply path?
Thanks for any idea!
73,
Tom, DK1IS
www.qrz.com/db/dk1is
--------------7559FF72431D71E07F12D648
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Content-Transfer-Encoding: quoted-printable
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Hello
Group,
Planning a new
single-ended Class E PA for my activities on the Dreamers Band
(8.27 kHz) two
questions came up - perhaps someone can help me:
-=C2=A0 Being
interested only in on-off-keying I=C2=B4m concerned about the capac=
itor
in parallel
to the power FET which in my case on VLF will be in the uF range.
If the DC
supply is on and without gate drive this capacitor is charged to
the DC supply
voltage. At the first positive gate pulse it discharges via the
drain-source-path,
the current being =C2=A0lim=
ited
only by
parasitc impedances - a poorly defined condition which usually has
to be
avoided. Does this mean that I have to apply drive continously and
key the DC
power supply only, perhaps synchronously to the next positive
drive pulse?
=C2=A0
-=C2=A0 =
span>Is
there any rule of thumb for the inductance of the rf choke in the
drain-power
supply path?
Thanks for
any idea!
73,
Tom, DK1IS
www.qrz.com/db/dk1is
--------------7559FF72431D71E07F12D648--