Return-Path: Received: from post.thorcom.com (post.thorcom.com [195.171.43.25]) by klubnl.pl (8.14.4/8.14.4/Debian-8+deb8u2) with ESMTP id w0RGtsTd012803 for ; Sat, 27 Jan 2018 17:55:56 +0100 Received: from majordom by post.thorcom.com with local (Exim 4.14) id 1efTg7-00059G-5k for rs_out_1@blacksheep.org; Sat, 27 Jan 2018 16:50:07 +0000 Received: from [195.171.43.32] (helo=relay1.thorcom.net) by post.thorcom.com with esmtp (Exim 4.14) id 1efTg1-000597-Jb for rsgb_lf_group@blacksheep.org; Sat, 27 Jan 2018 16:50:01 +0000 Received: from mail-wm0-x233.google.com ([2a00:1450:400c:c09::233]) by relay1.thorcom.net with esmtps (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.89) (envelope-from ) id 1efTfx-0003kq-Bm for rsgb_lf_group@blacksheep.org; Sat, 27 Jan 2018 16:50:00 +0000 Received: by mail-wm0-x233.google.com with SMTP id t74so6691004wme.3 for ; Sat, 27 Jan 2018 08:49:57 -0800 (PST) X-DKIM-Result: Domain=gmail.com Result=Good and Known Domain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Duz1uc2gNFWZALDH8shscQTUyT5yesWb5sQXkzAn8IQ=; b=gYBLkmE0GdnP0O90BqktPcmL9i8XPV3JNms1eiWQmpg8uhDTGm1zPEZNCId6rFY8BB yu4KHA1bQJdRQzNHiQE5qCoqMxNjZsMV8dhIUp8DTo8ulkwaMHu1n4K0gC+OCDdx/oru IRjydXb2J3F9RGhTlhi9TY5//9vkscJsBZoVEz1WrtMufbps8ThkFgBvM6rkuk2h9Fzh hPhxYMTgeS64wSlkSsX4UiFyYYTp75GXN2/X/0g/qRjl4e9ACJtZBdO2LdAxszJ+fIZG 6M8EodfsJiFUGXXI6fVuFupFajOI3pZFR5meWma5SwdREf1JNGH4IyROnbPsMpiicIkX IQYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Duz1uc2gNFWZALDH8shscQTUyT5yesWb5sQXkzAn8IQ=; b=H8iMKvFbvarIbFOi4xMrMad3wDZ/81Os+kuCcBnPad1c46iO7HwKjYs65wIA3FW5Ta 2iCoF4O0twczQzveCecuj2upSR2E/OqLgpsD5+LTv8dWnZq/0IA8M9kWVd4w/JvO+eYq ZCV6/cjdAvOJb7pA3E1RcE5X8LrQMe2umz3qOUTw+soMQ7Ri6joUg4Ln/JoGF5Gh1Dg2 BS9vdEJMmKLqtjvOK9DywEPOvohejw7OjisSXZ4ISvEq6J/R+xp0hAwkmPVTqs7KbcIb 64S2pCeDDt1OsJdwMLgBnv9TSqDxl059UO8VCe8z/gEMs8IErQKgdsLjMIhFJChIfihg gYew== X-Gm-Message-State: AKwxytd/CdjqGtK7oVFYdsAoMSd9PTedvJDfBzCewwoZr9Xi2TRtxvW5 OR5hNOpYY9E7cbWh8tDOxNUXO03M9lHVM60rB/c0mQ== X-Google-Smtp-Source: AH8x225rdY3aSDC/TOV3cl/KcdWF04pNcIfi4whBxe2mSdco7g9kGZr3xWhILETSoqcqbG6fMgHd98t9b0qXsfyJ6YI= X-Received: by 10.80.189.139 with SMTP id y11mr28168337edh.122.1517071796373; Sat, 27 Jan 2018 08:49:56 -0800 (PST) MIME-Version: 1.0 Received: by 10.80.179.198 with HTTP; Sat, 27 Jan 2018 08:49:55 -0800 (PST) In-Reply-To: <7010021367.20180127161312@gmail.com> References: <1371247928.20180126134524@gmail.com> <1397698645.2553258.1516983835152.JavaMail.open-xchange@oxbe7.tb.ukmail.iss.as9143.net> <686847880.20180126193617@gmail.com> <791320206.20180126221646@gmail.com> <7010021367.20180127161312@gmail.com> From: Andy Talbot Date: Sat, 27 Jan 2018 16:49:55 +0000 Message-ID: To: LineOne Cc: Chris Wilson X-Spam-Score: 1.0 (+) X-Spam-Report: Spam detection software, running on the system "relay1.thorcom.net", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Looking at the schematic, I see a 74AC74 divider is used which works at over 100MHz clock frequency. You are hitting its edge triggered clock inputs with low frequency waveform (461kHz) with a slow and indeterminate rise time caused by crude semi-linear amplification plus clipping. It really is no wonder the system is not driving the divider properly. That sluggish edge has to hit the D input on both flip-flops and cause them to toggle together. I'm surprised it even appears to work at HF where the design originated. [...] Content analysis details: (1.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (andy.g4jnt[at]gmail.com) 0.0 HTML_MESSAGE BODY: HTML included in message 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid 1.0 FREEMAIL_REPLY From and body contain different freemails X-Scan-Signature: 14522a7d8bfffcae5e92e35059f18ae1 Subject: Re: LF: Softrock RX divider IC problem, unexpected frequency out Content-Type: multipart/alternative; boundary="f4030438b338858f840563c4cdb4" X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on post.thorcom.com X-Spam-Level: X-Spam-Status: No, hits=0.6 required=5.0 tests=HTML_20_30, HTML_FONTCOLOR_UNSAFE,HTML_MESSAGE autolearn=no version=2.63 X-SA-Exim-Scanned: Yes Sender: owner-rsgb_lf_group@blacksheep.org Precedence: bulk Reply-To: rsgb_lf_group@blacksheep.org X-Listname: rsgb_lf_group X-SA-Exim-Rcpt-To: rs_out_1@blacksheep.org X-SA-Exim-Scanned: No; SAEximRunCond expanded to false --f4030438b338858f840563c4cdb4 Content-Type: text/plain; charset="UTF-8" Looking at the schematic, I see a 74AC74 divider is used which works at over 100MHz clock frequency. You are hitting its edge triggered clock inputs with low frequency waveform (461kHz) with a slow and indeterminate rise time caused by crude semi-linear amplification plus clipping. It really is no wonder the system is not driving the divider properly. That sluggish edge has to hit the D input on both flip-flops and cause them to toggle together. I'm surprised it even appears to work at HF where the design originated. That design with no proper logic level squarer is just asking for trouble and I'd be surprised if you ever get it to work properly. It might, perhaps, if the divider were changed to a slower 74HC74 device, but that's a bit speculative; it may be just as bad. I would suggest you stop fiddling about with component values, trying to frig an unsuitable design. You MUST feed a proper shaped logic level to such high speed divider chips. There really is no getting round that fact. They won't work properly otherwise - just look at the specifications for AC series logic. You can keep the simple single transistor buffer, but use its output to feed the input of a shaping gate. A Schmitt like a 74HC14 (a package that has 6 suitable gates) ought to do you nicely. Bias the input mid way between its two threshold voltage - these are different for HC and HCT family devices, so consult the data sheet. AC couple your RF to the mid-biassed input and connect output to the divider. Look at the gate output on a scope and you'll have a beautiful square wave width lovely vertical edges and perfect quadrature generation however low a drive signal you put in. Andy G4JNT On 27 January 2018 at 16:13, Chris Wilson wrote: > > > Hello all. > > Today when powered up there was rarely any output from the divider at > all, so I started again. > > I decided to try two things, build a little test rig with a spare xtal > of the same 461.5kHz as the one in the RX with the same C10 at 3900pF > and C11 at 2700pF on a bit of pcb and excite it at 1v P to P sine wave > from my sig gen around the xtal frequency and look at the output on > the scope. That failed abysmally, no change in display, thinking about > it maybe it's due to the big capacitances involved? > > Anyway, back to the RX. C12 at 680pF, C10 at 3900pF and C11 at 2700pF. > Waveforms taken with scope at DC coupling, but V scaling changes. I > believe (dangerous with my lack of knowledge..) that C10 to base of Q1 > is good. Base of Q2 looks ok. But with R16 at the recommended 10K I > see half a sine wave at the emitter of Q2. With the original 20k (I > don't have the oddball 20.1k around) the waveform is still part > complete and of a much lower amplitude. > > Is this a bias issue with Q2 or something else please? > > > > I hope the file names are self explanatory! Note that V axis scaling > changes in some shots!! > > > Thank you for all your help! > > > > > > The schematic for the modded Softrock Lite II in question: > > http://www.gatesgarth.com/schematic2.jpg > > > Scope screen captures: > > http://www.gatesgarth.com/lf-base-q1.jpg > > http://www.gatesgarth.com/lf-emitter-q1.jpg > > http://www.gatesgarth.com/lf-base-q2.jpg > > http://www.gatesgarth.com/lf-emitter-q2-r16-at-10k.jpg > > http://www.gatesgarth.com/lf-emitter-q2-r16-at-22k.jpg > > > Friday, January 26, 2018, 11:52:20 PM, you wrote: > > > Hi again > > > > Well all seems well if you are getting a good wave at the flip flop > > output. Just a comment about your input wave forms yes the MF does > > show a second harmonic petty low and as you have said the MF version > > works OK. Please remember a square wave is in fact and infinite > > number of harmonic frequencies so this is not an issue the dominant > > wave is overwhelmingly the fundamental so that will be processed > > into a square wave by the Flip Flop. If the drive to the > > multiplexer is good as you say (I can not open the JPG but it > > doesn't matter) it sounds like the local oscillator divider chain is > > correct. I can only conclude the instability reported is at the > > oscillator suggest you concentrate on that as a source of your > > problem. ..... I have run out of ideas. > > > > Anyway good luck and please report the solution there are a lot of > > people very interested. 73 petefmt > > > > > > > -- > Best regards, > Chris mailto:dead.fets@gmail.com > > > --f4030438b338858f840563c4cdb4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Looking at the schematic, I see a 74AC74 divider is used w= hich works at over 100MHz clock frequency.=C2=A0 =C2=A0You are hitting its = edge triggered clock inputs with low frequency waveform (461kHz) with=C2=A0= a slow and indeterminate rise time caused by crude semi-linear amplificati= on plus clipping.=C2=A0 =C2=A0It really is no wonder the system is not driv= ing the divider properly.=C2=A0 =C2=A0 That sluggish edge has to hit the D = input on both flip-flops and cause them to toggle together.=C2=A0 =C2=A0I&#= 39;m surprised it even appears to work at HF where the design originated.
That design with no proper logic level squarer is just as= king for trouble and I'd be surprised if you ever get it to work proper= ly.=C2=A0 It might, perhaps, if the divider were changed to a slower 74HC74= device, but that's a bit speculative;=C2=A0 it may be just as bad.

=C2=A0I would suggest you stop fiddling about with co= mponent values, trying to frig an unsuitable design.=C2=A0 You MUST feed =C2=A0a proper shaped logic level to such high speed divider chips.=C2=A0 Th= ere really is no getting round that fact.=C2=A0 They won't work properl= y otherwise - just look at the specifications for AC series logic.

You can keep the simple single transistor buffer, b= ut use its output to feed the input of a shaping gate.=C2=A0 A Schmitt like= a 74HC14 (a package that has 6 suitable gates) ought to do you nicely.=C2= =A0 =C2=A0 Bias the input mid way between its two threshold voltage - these= are different for HC and HCT family devices, so consult the data sheet.=C2= =A0 AC couple your RF to the mid-biassed input and connect output to the di= vider. =C2=A0 =C2=A0 =C2=A0Look at the gate output on a scope and you'll have a beaut= iful square wave width lovely vertical edges and perfect quadrature generat= ion however low a drive signal you put in.

Andy=C2= =A0 G4JNT

On 2= 7 January 2018 at 16:13, Chris Wilson <dead.fets@gmail.com> wrote:


Hello all.

Today=C2=A0 when powered up there was rarely any output from the divider at=
all, so I started again.

I decided to try two things, build a little test rig with a spare xtal
of the same 461.5kHz as the one in the RX with the same C10 at 3900pF
and C11 at 2700pF on a bit of pcb and excite it at 1v P to P sine wave
from my sig gen around the xtal frequency and look at the output on
the scope. That failed abysmally, no change in display, thinking about
it maybe it's due to the big capacitances involved?

Anyway, back to the RX. C12 at 680pF, C10 at 3900pF and C11 at 2700pF.
Waveforms taken with scope at DC coupling, but V scaling changes. I
believe (dangerous with my lack of knowledge..) that C10 to base of Q1
is good. Base of Q2 looks ok. But with R16 at the recommended 10K I
see half a sine wave at the emitter of Q2. With the original 20k (I
don't have the oddball 20.1k around) the waveform is still part
complete and of a much lower amplitude.

Is this a bias issue with Q2 or something else please?



I=C2=A0 hope=C2=A0 the file names are self explanatory! Note that V axis sc= aling
changes in some shots!!


Thank you for all your help!





The schematic for the modded Softrock Lite II in question:

=C2=A0 =C2=A0 =C2=A0 http://www.gatesgarth.com/schemati= c2.jpg


=C2=A0Scope screen captures:

=C2=A0 http://www.gatesgarth.com/lf-base-q1.jpg

=C2=A0 http://www.gatesgarth.com/lf-emitter-q1.jpg

=C2=A0 http://www.gatesgarth.com/lf-base-q2.jpg

=C2=A0 http://www.gatesgarth.com/lf-emitt= er-q2-r16-at-10k.jpg

=C2=A0 http://www.gatesgarth.com/lf-emitt= er-q2-r16-at-22k.jpg


Friday, January 26, 2018, 11:52:20 PM, you wrote:

> Hi again


> Well all seems well if you are getting a good wave at the flip flop > output. Just a comment about your input wave forms yes the MF does
> show a second harmonic petty low and as you have said the MF version > works OK. Please remember a square wave is in fact and infinite
> number of harmonic frequencies so this is not an issue the dominant > wave is overwhelmingly the fundamental so that will be processed
> into a square wave by the Flip Flop.=C2=A0 If the drive to the
> multiplexer is good as you say (I can not open the JPG but it
> doesn't matter) it sounds like the local oscillator divider chain = is
> correct. I can only conclude the instability reported is at the
> oscillator suggest you concentrate on that as a source of your
> problem. ..... I have run out of ideas.


> Anyway good luck and please report the solution there=C2=A0are a lot o= f
> people very interested. 73 petefmt






--
Best regards,
=C2=A0Chris=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 mailto:dead.fets@gmail.com



--f4030438b338858f840563c4cdb4--