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[82.70.254.222]) by smtp.gmail.com with ESMTPSA id f13sm11265252wre.84.2018.01.29.05.47.45 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 29 Jan 2018 05:47:46 -0800 (PST) Date: Mon, 29 Jan 2018 13:47:44 +0000 From: Chris Wilson X-Priority: 3 (Normal) Message-ID: <1391611381.20180129134744@gmail.com> To: LineOne CC: dead.fets@gmail.com In-Reply-To: References: <1371247928.20180126134524@gmail.com> <1397698645.2553258.1516983835152.JavaMail.open-xchange@oxbe7.tb.ukmail.iss.as9143.net> <686847880.20180126193617@gmail.com> <791320206.20180126221646@gmail.com> <7010021367.20180127161312@gmail.com> MIME-Version: 1.0 X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "relay1.thorcom.net", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Hello Andy, I am having to admit defeat and defer to your diagnosis, I have managed to lift two pads removing the SOIC divider IC again, so await some bare boards from the US. I will modify one to take out the signal after the buffer Q2 and take it to a Schmitt IC. Can you say what AC coupling cap value I should use? 680pF like the one between the oscillator and the buffer? Will pretty short wires to a small standalone PCB work, then the same back to the RX board? I would imagine so at such a low frequency? I would also like to try a DDS source for a variable LO and get one built for VLF, did yours work OK down there? Many thanks for your help, it was frustrating knowing N1BUG has a similar RX working fine without the Schmitt trigger, but I kind of suspect my changing the divider chip to one which may be faster has screwed something which was on the edge to start with. Problem is the markings on the original IC do not show up what it initially was on Google, soI can't directly compare specs. [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (dead.fets[at]gmail.com) 0.0 T_DKIM_INVALID DKIM-Signature header exists but is not valid X-Scan-Signature: 7a302ec14fb4a62f16f049454b6dc54d Subject: Re: LF: Softrock RX divider IC problem, unexpected frequency out Content-Type: text/plain; charset=utf-8 X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on post.thorcom.com X-Spam-Level: X-Spam-Status: No, hits=0.8 required=5.0 tests=PRIORITY_NO_NAME autolearn=no version=2.63 X-SA-Exim-Scanned: Yes Sender: owner-rsgb_lf_group@blacksheep.org Precedence: bulk Reply-To: rsgb_lf_group@blacksheep.org X-Listname: rsgb_lf_group X-SA-Exim-Rcpt-To: rs_out_1@blacksheep.org X-SA-Exim-Scanned: No; SAEximRunCond expanded to false Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by klubnl.pl id w0TDs2DT020533 Hello Andy, I am having to admit defeat and defer to your diagnosis, I have managed to lift two pads removing the SOIC divider IC again, so await some bare boards from the US. I will modify one to take out the signal after the buffer Q2 and take it to a Schmitt IC. Can you say what AC coupling cap value I should use? 680pF like the one between the oscillator and the buffer? Will pretty short wires to a small standalone PCB work, then the same back to the RX board? I would imagine so at such a low frequency? I would also like to try a DDS source for a variable LO and get one built for VLF, did yours work OK down there? Many thanks for your help, it was frustrating knowing N1BUG has a similar RX working fine without the Schmitt trigger, but I kind of suspect my changing the divider chip to one which may be faster has screwed something which was on the edge to start with. Problem is the markings on the original IC do not show up what it initially was on Google, soI can't directly compare specs. Saturday, January 27, 2018, 7:17:31 PM, you wrote: > I never documented the mods made to my Softrock [clone] to get it > down to low frequencies, so took a look inside to see what I did.  > I see I used an LM393 comparator and it took a few minutes to > realise why I did that instead of a Schmitt biassed half way as suggested here. > I am deriving my LO from a DDS source, an AD9852, which only > delivers about 2 V p-p.   This was not enough to reliably swing > between the thresholds of a 74AC Schmitt which lie roughly at  1.5 > and 3.5 Volts.   The LM393 has a much lower hysteresis of around > 400mV so worked with lower input.   I wanted to get it down to 5kHz RF (20kHz LO input). > As you will be using the Q2 buffer, there should be no problem > getting a 2.5V to 3V swing for hitting the Schmitt thesholds. > Andy  G4JNT > On 27 January 2018 at 16:49, Andy Talbot wrote: > Looking at the schematic, I see a 74AC74 divider is used which > works at over 100MHz clock frequency.   You are hitting its edge > triggered clock inputs with low frequency waveform (461kHz) with  a > slow and indeterminate rise time caused by crude semi-linear > amplification plus clipping.   It really is no wonder the system is > not driving the divider properly.    That sluggish edge has to hit > the D input on both flip-flops and cause them to toggle together.  > I'm surprised it even appears to work at HF where the design originated. > That design with no proper logic level squarer is just asking for > trouble and I'd be surprised if you ever get it to work properly.  > It might, perhaps, if the divider were changed to a slower 74HC74 > device, but that's a bit speculative;  it may be just as bad. >  I would suggest you stop fiddling about with component values, > trying to frig an unsuitable design.  You MUST feed  a proper > shaped logic level to such high speed divider chips.  There really > is no getting round that fact.  They won't work properly otherwise - > just look at the specifications for AC series logic. > You can keep the simple single transistor buffer, but use its > output to feed the input of a shaping gate.  A Schmitt like a 74HC14 > (a package that has 6 suitable gates) ought to do you nicely.    > Bias the input mid way between its two threshold voltage - these are > different for HC and HCT family devices, so consult the data sheet.  > AC couple your RF to the mid-biassed input and connect output to the > divider.      Look at the gate output on a scope and you'll have a > beautiful square wave width lovely vertical edges and perfect > quadrature generation however low a drive signal you put in. > Andy  G4JNT > On 27 January 2018 at 16:13, Chris Wilson wrote: > > Hello all. > > Today  when powered up there was rarely any output from the divider at > all, so I started again. > > I decided to try two things, build a little test rig with a spare xtal > of the same 461.5kHz as the one in the RX with the same C10 at 3900pF > and C11 at 2700pF on a bit of pcb and excite it at 1v P to P sine wave > from my sig gen around the xtal frequency and look at the output on > the scope. That failed abysmally, no change in display, thinking about > it maybe it's due to the big capacitances involved? > > Anyway, back to the RX. C12 at 680pF, C10 at 3900pF and C11 at 2700pF. > Waveforms taken with scope at DC coupling, but V scaling changes. I > believe (dangerous with my lack of knowledge..) that C10 to base of Q1 > is good. Base of Q2 looks ok. But with R16 at the recommended 10K I > see half a sine wave at the emitter of Q2. With the original 20k (I > don't have the oddball 20.1k around) the waveform is still part > complete and of a much lower amplitude. > > Is this a bias issue with Q2 or something else please? > > > > I  hope  the file names are self explanatory! Note that V axis scaling > changes in some shots!! > > > Thank you for all your help! > > > > > > The schematic for the modded Softrock Lite II in question: > >       http://www.gatesgarth.com/schematic2.jpg > > >  Scope screen captures: > >   http://www.gatesgarth.com/lf-base-q1.jpg > >   http://www.gatesgarth.com/lf-emitter-q1.jpg > >   http://www.gatesgarth.com/lf-base-q2.jpg > >   http://www.gatesgarth.com/lf-emitter-q2-r16-at-10k.jpg > >   http://www.gatesgarth.com/lf-emitter-q2-r16-at-22k.jpg > > > Friday, January 26, 2018, 11:52:20 PM, you wrote: > >> Hi again > > >> Well all seems well if you are getting a good wave at the flip flop >> output. Just a comment about your input wave forms yes the MF does >> show a second harmonic petty low and as you have said the MF version >> works OK. Please remember a square wave is in fact and infinite >> number of harmonic frequencies so this is not an issue the dominant >> wave is overwhelmingly the fundamental so that will be processed >> into a square wave by the Flip Flop.  If the drive to the >> multiplexer is good as you say (I can not open the JPG but it >> doesn't matter) it sounds like the local oscillator divider chain is >> correct. I can only conclude the instability reported is at the >> oscillator suggest you concentrate on that as a source of your >> problem. ..... I have run out of ideas. > > >> Anyway good luck and please report the solution there are a lot of >> people very interested. 73 petefmt > > > > > > > -- > Best regards, >  Chris                            mailto:dead.fets@gmail.com > > > > -- Best regards, Chris mailto:dead.fets@gmail.com