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From: Andy Talbot <andy.g4jnt@gmail.com>
Date: Sat, 3 Jun 2017 17:28:45 +0100
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To: rsgb_lf_group@blacksheep.org
Subject: Re: LF: For today the FETs survived... - not enough gate voltage?
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Interesting thought.

Checked my own design (the QEX article is the only remaining
documentation!) and checked I  also have a 1:1+1 driver transformer.
But I do use a 15V rail for the driver, so +/- 7.5V which is a bit more
than Marco's

But never considered that ...

Andy  G4JNT


On 3 June 2017 at 17:13, Markus Vester <markusvester@aol.com> wrote:

> Hi Marco,
>
> looking at your schematic, I think the gate drive may be too low. Ideally
> the driver will make 12 V peak-peak, or +-6V at the gate (probably slight=
ly
> less in reality, e.g. 5 V). This may not be enough to turn the FETs fully
> on. So when increasing the drain suppy voltage beyond a certain limit, th=
ey
> will go out of saturation and limit the available output current. In that
> case you won't get more output power but only much more dissipation. Also
> the output impedance will go from low (voltage-source) to high
> (current-source), which could explain the changing frequency response.
>
> I would recommend to double the turns ratio of the gate transformer (e.g.
> 10:20:20).
>
> 73, Markus (DF6NM)
>
> -----Urspr=C3=BCngliche Mitteilung-----
> Von: marcocadeddu <marcocadeddu@tin.it>
> An: rsgb_lf_group <rsgb_lf_group@blacksheep.org>
> Verschickt: Sa, 3. Jun 2017 16:46
> Betreff: R: Re: R: Re: LF: Re: I: Fw: For today the FETs survived...
>
> Hi Stefan,
>
> and thank you :-) so you have too something to mumble while sending
> VLF SMS ;-)
> There is nothing really new.. I started from an avalable
> chassis with on board a PS giving 180Vdc (1200W) and assembled the
> Andy's half bridge 700W switching PA and before give it the full power
> I'm checking with lower DC supply. Attached you see the schematic with
> some change at the moment..
> The output xfmr has 7T/19T, the coil of the guard circuit is not
> connected (now is in serie with L2) and the resonating caps now are
> 5x1000pF in parallel.
> The aim is finally with 180Vdc of supply have an output of 0,5=C3=B71kW
> but.... as you probably red in the previous messages, from 10 to 30Vdc
> the PA runs, at low power of course (up to 15W), and complies the
> calculations; with supply between 30 and 50 Vdc the output go down to a
> couple of W.
> I made several trials it the last days, changing the core of the xfmr,
> the turn ratio, the kind of capacitators but nothing changes (or at
> least the change are within a fraction of dB).
>
> that's the sad history Stefan...
> All thoughts and suggestions are welcome! (including go to fish ;-)) )
> Marco
>
> ...
>
>

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<div dir=3D"ltr">Interesting thought.<div><br><div>Checked my own design (t=
he QEX article is the only remaining documentation!) and checked I =C2=A0al=
so have a 1:1+1 driver transformer.</div><div>But I do use a 15V rail for t=
he driver, so +/- 7.5V which is a bit more than Marco&#39;s</div><div><br><=
/div><div>But never considered that ...</div><div><br></div><div>Andy =C2=
=A0G4JNT</div><div><br></div><div class=3D"gmail_extra"><br><div class=3D"g=
mail_quote">On 3 June 2017 at 17:13, Markus Vester <span dir=3D"ltr">&lt;<a=
 href=3D"mailto:markusvester@aol.com" target=3D"_blank">markusvester@aol.co=
m</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quote" style=3D"margi=
n:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style=3D"fon=
t-size:10pt;font-family:arial,helvetica,sans-serif;color:black"><div style=
=3D"color:black;font-family:arial,helvetica,sans-serif;font-size:10pt">Hi M=
arco,<br><br>looking at your schematic, I think the gate drive may be too l=
ow. Ideally the driver will make 12 V peak-peak, or +-6V at the gate (proba=
bly slightly less in reality, e.g. 5 V). This may not be enough to turn the=
 FETs fully on. So when increasing the drain suppy voltage beyond a certain=
 limit, they will go out of saturation and limit the available output curre=
nt. In that case you won&#39;t get=C2=A0more output power but only=C2=A0muc=
h more=C2=A0dissipation. Also the output impedance will go from low (voltag=
e-source)=C2=A0to high (current-source), which could=C2=A0explain the chang=
ing frequency response. <br><br>I would recommend to=C2=A0double the turns =
ratio of the gate transformer (e.g. 10:20:20).<br><br>73, Markus (DF6NM)<br=
><br>-----Urspr=C3=BCngliche Mitteilung----- <br>Von: marcocadeddu &lt;<a h=
ref=3D"mailto:marcocadeddu@tin.it" target=3D"_blank">marcocadeddu@tin.it</a=
>&gt;<br>An: rsgb_lf_group &lt;<a href=3D"mailto:rsgb_lf_group@blacksheep.o=
rg" target=3D"_blank">rsgb_lf_group@blacksheep.org</a>&gt;<br>Verschickt: S=
a, 3. Jun 2017 16:46<br>Betreff: R: Re: R: Re: LF: Re: I: Fw: For today the=
 FETs survived...<br><br></div>Hi Stefan,<br><br>and thank you :-) so you h=
ave too something to mumble while sending <br>VLF SMS ;-)<br>There is nothi=
ng really new.. I started from an avalable <br>chassis with on board a PS g=
iving 180Vdc (1200W) and assembled the <br>Andy&#39;s half bridge 700W swit=
ching PA and before give it the full power <br>I&#39;m checking with lower =
DC supply. Attached you see the schematic with <br>some change at the momen=
t..<br>The output xfmr has 7T/19T, the coil of the guard circuit is not <br=
>connected (now is in serie with L2) and the resonating caps now are <br>5x=
1000pF in parallel.<br>The aim is finally with 180Vdc of supply have an out=
put of 0,5=C3=B71kW <br>but.... as you probably red in the previous message=
s, from 10 to 30Vdc <br>the PA runs, at low power of course (up to 15W), an=
d complies the <br>calculations; with supply between 30 and 50 Vdc the outp=
ut go down to a <br>couple of W.<br>I made several trials it the last days,=
 changing the core of the xfmr, <br>the turn ratio, the kind of capacitator=
s but nothing changes (or at <br>least the change are within a fraction of =
dB).<br><br>that&#39;s the sad history Stefan...<br>All thoughts and sugges=
tions are welcome! (including go to fish ;-)) )<br>Marco<br><br>...<br><br>=
</div></blockquote></div><br></div></div></div>

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