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Date: Sun, 6 Dec 2015 11:02:21 +0000
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From: Andy Talbot <andy.g4jnt@gmail.com>
To: rsgb_lf_group@blacksheep.org
Subject: Re: LF: EbNaut / Coherent PSK reception with SDR (-IQ) or similar radios
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Status: O

This is a synth that would do it - if you were to frig the VCO to go
down to that frequency - and more to the point, could still get the
MC45170 chip.   http://www.g4jnt.com/VHF_Synth_Module.pdf

These days there are not many synth chips that will work directly with
low frequency RF inputs.   Any number are out there with 500MHz
minimum, but only a small subset have output dividers, so any PLL
synth solution for HF often need sextra output dividers

Andy  G4JNT

On 6 December 2015 at 10:46, Andy Talbot <andy.g4jnt@gmail.com> wrote:
> I did it with a simple PLL
> VCO running at 66.6...MHz divided by 30.   10MHz reference input divided by 3,
> Phase comparator running at 333.333...kHz
>
> I used a superannuated obsolete MC145170 chip, but there are a
> plethora of modern PLL chips out now that will do it for you.
> Several types even have internal VCOs so you can have a one chip
> solution (plus the programmer, of course)
>
> Andy  G4JNT
>
>
> On 6 December 2015 at 10:33, Wolfgang Büscher <dl4yhf@freenet.de> wrote:
>> Greetings all,
>>
>> After trying a couple of modifications to my SDR-IQ, I found the following
>> site ..
>>
>> http://g4hup.com/SDRlock.html
>>
>> .. which describes how to lock the 66.6667 MHz 'ADC clock' in the SDR-IQ to
>> an external 10 MHz reference.
>>
>> Does anyone here have own experiences with this, or a similar circuit ?
>> Dividing the 10 MHz reference by three, and subtracting that from 10 MHz
>> multiplied by 7 sounds intriguing, but a multi-pole crystal ladder filter to
>> 'clean up' the resulting 66.6666666 MHz signal is easier said than done
>> (..lacking such crystals in the junk box).
>>
>> 73,
>>   Wolf DL4YHF .
>>
>>