Return-Path: X-Spam-DCC: paranoid 1233; Body=3 Fuz1=3 Fuz2=2 X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on lipkowski.org X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DNS_FROM_AHBL_RHSBL, HTML_30_40,HTML_MESSAGE autolearn=no version=3.1.3 Received: from post.thorcom.com (post.thorcom.com [195.171.43.25]) by paranoid.lipkowski.org (8.13.7/8.13.7) with ESMTP id tAFJa9du005520 for ; Sun, 15 Nov 2015 20:36:09 +0100 Received: from majordom by post.thorcom.com with local (Exim 4.14) id 1Zy2yf-0004yc-Vr for rs_out_1@blacksheep.org; Sun, 15 Nov 2015 19:28:41 +0000 Received: from [195.171.43.32] (helo=relay1.thorcom.net) by post.thorcom.com with esmtp (Exim 4.14) id 1Zy2yf-0004yT-GR for rsgb_lf_group@blacksheep.org; Sun, 15 Nov 2015 19:28:41 +0000 Received: from mail-wm0-f50.google.com ([74.125.82.50]) by relay1.thorcom.net with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86) (envelope-from ) id 1Zy2xb-0001Ig-FO for rsgb_lf_group@blacksheep.org; Sun, 15 Nov 2015 19:28:40 +0000 Received: by wmvv187 with SMTP id v187so147494370wmv.1 for ; Sun, 15 Nov 2015 11:27:19 -0800 (PST) X-DKIM-Result: Domain=gmail.com Result=Good and Known Domain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; bh=cIUQQeFtbei6JWQQX+PzGtzIp5VtVfvYpFTlavIVI8g=; b=h8FTEUfA1mwh1WKlemsJ2rxbCCUPic0jN2kRI6zMd3QJxKrRjWzy/PrttCJOGNl7AA 8cC2Sh+BzJKwlMuGHWcEfUDq0OhsAcO6LfrWcS141aP5OfeUG9Y/LfYd28XTy8vYR+tp v20FDszu/qg5L/GPC8mCHxInFYxMEZEWuVmCASZetmYfUn0zWDA3fOe54jtt1iOZpyHZ iS6cUEzvxmyvVqmavJsg2O2XXHoGyxRMJI6WJpMzawXBlfJ6hie/mOR/rnx0nkg0/i+Y e1tqHcDMWl9NlXkvmSy4GeT+keo7bkBXP687vJjTyoSdAvA3lBtPpz1GsNNwiIuTLt8q jPSw== MIME-Version: 1.0 X-Received: by 10.28.6.142 with SMTP id 136mr15851048wmg.9.1447615639394; Sun, 15 Nov 2015 11:27:19 -0800 (PST) Received: by 10.28.130.139 with HTTP; Sun, 15 Nov 2015 11:27:19 -0800 (PST) In-Reply-To: <1D1F983E9B4640778B8AF51C5673868D@White> References: <56478990.2@abelian.org> <1D1F983E9B4640778B8AF51C5673868D@White> Date: Sun, 15 Nov 2015 19:27:19 +0000 Message-ID: From: Andy Talbot To: rsgb_lf_group@blacksheep.org X-Scan-Signature: f9f85a03ab18710b130c40acc03380f0 Subject: Re: LF: Ramped BPSK Content-Type: multipart/alternative; boundary=001a11442706f51f540524994799 X-SA-Exim-Scanned: Yes Sender: owner-rsgb_lf_group@blacksheep.org Precedence: bulk Reply-To: rsgb_lf_group@blacksheep.org X-Listname: rsgb_lf_group X-SA-Exim-Rcpt-To: rs_out_1@blacksheep.org X-SA-Exim-Scanned: No; SAEximRunCond expanded to false X-Scanned-By: MIMEDefang 2.56 on 10.1.3.10 Status: O X-Status: X-Keywords: X-UID: 5097 --001a11442706f51f540524994799 Content-Type: text/plain; charset=UTF-8 I quite deliberately send the phase transitions in opposite direction to prevent a continuous rotation, meaning a net frequency shift. When going from '0' to '1' the programmed phase is set to 0x2000 - the value it would have been if going from '1' to '0' (0x2000 beingbthe value needed for 180 degree phase shift in the 14 bit register of the AD9852) My rotary encoder / LCD system on the deliberately shows the hex code sent to the DDS for precisely that reason. But in a 48 bit frequency register that is a bit OTT, as 48 bits give a resolution better than the current world standard for time / frequency precision, and the maths used for setting 0.01Hz steps allow a rather worse few parts in 10^-9 Andy G4JNT On 15 November 2015 at 13:30, Markus Vester wrote: > >> the humiliation of being a significant part of a mHz off QRG, > > ;-) The upside is that such offsets are perfectly deterministic. > Knowing your clocking scheme, and assuming that your controller always > rounds to the next-lower frequency word, we find that 137477 is low at -629 > uHz low, and 137777 only -91 uHz, apparently matching observations. If you > had chosen nearest integer rounding, 137477 would have been somewhat closer > at +244 uHz ;-) > > In the context of using PSK / Wolf modes with nonlinear amplifiers, DL4YHF > had long ago included a continuous phase ramp option in SpecLab's digimode > modulator. My conceptual problem is that I never know which way to swing > around - at each transition one has to make an arbitrary decision between a > low or high frequency spike... > > > All the best, > Markus (DF6NM) > > > > *From:* jcraig@mun.ca > *Sent:* Saturday, November 14, 2015 9:47 PM > *To:* rsgb_lf_group@blacksheep.org > *Subject:* Re: LF: Ramped BPSK > > Hi Andy, > > I was about to solder a dpdt relay across a transformer until I saw your > posting. The DDS here is the 9851 and the 40 bits are loaded serially. > If bits 35-39 are changed from 00000 to 00010 the phase will change by > 180 degrees and so the soldering iron can be switched off? > > An AD9852 would spare me the humiliation of being a significant > part of a mHz off QRG, but these chips seem hard to get. Markus was > right about the resolution. The DDS is clocked at 10 MHz with the > x6 multiplier. The output is then divided by 16. The resolution is just > under 1 mHz and so the frequency error depends on the output frequency. > > 73 Joe VO1NA > > > > On Sat, 14 Nov 2015, Andy Talbot wrote: > > > Try the Anlaog Devices web site - www.analog.com > > > > I built my own PCB, http://www.g4jnt.com/AD9852module.pdf (PCBs are > no > > longer available for that, though). That particular DDS is a bit out of > > date now. I use it for this job as I have a few modules left, and it is > > one of the few devices with both a 48 bit frequency setting register and > > amplitude programmability. > > > > Andy G4JNT > > > > On 14 November 2015 at 19:20, Paul Nicholson > wrote: > > > >> > >> With sufficiently brief phase steps, those discrete sidebands > >> will fall outside the loading coil bandwidth and be well > >> attenuated. > >> > >> But, does that bring back the audible clicks from the PA > >> and coil? > >> > >> I'm keen to have a play with these DDS chips. Is there a > >> recommended evaluation board? > >> > >> -- > >> Paul Nicholson > >> -- > >> > >> > > > > --001a11442706f51f540524994799 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
I quite deliberately send the phase transitions in opposit= e direction to prevent a continuous rotation, meaning a net frequency shift= . =C2=A0 When going from '0' to '1' the programmed phase is= set to 0x2000 - the value it would have been if going from '1' to = '0' =C2=A0(0x2000 beingbthe value needed for 180 degree phase shift= in the 14 bit register of the AD9852)

My rotary encoder= / LCD system on the deliberately shows the hex code sent to the DDS for pr= ecisely that reason.=C2=A0 But in a 48 bit frequency register that is a bit= OTT, as 48 bits give a resolution better than the current world standard f= or time / frequency precision, and the maths used for setting 0.01Hz steps = =C2=A0allow a rather worse few parts in 10^-9

Andy= =C2=A0G4JNT

O= n 15 November 2015 at 13:30, Markus Vester <markusvester@aol.com>= ; wrote:
>> the=20 humiliation of being a significant part of a mHz off QRG,
=C2=A0
;-)=C2=A0=C2=A0 The=20 upside is that=C2=A0such offsets are perfectly deterministic. Knowing your= =20 clocking scheme, and assuming that your controller always rounds to the=20 next-lower frequency word, we=C2=A0find that=C2=A0137477 is low at -629 uHz= =20 low,=C2=A0and 137777=C2=A0only=C2=A0=C2=A0-91 uHz, apparently=20 matching=C2=A0observations. If you had=C2=A0chosen=C2=A0nearest integer=20 rounding, 137477 would have been somewhat closer at +244 uHz ;-)
=C2=A0
In the context of using PSK / Wolf mod= es with=20 nonlinear amplifiers, DL4YHF had=C2=A0long ago included a continuous phase = ramp=20 option in SpecLab's digimode modulator. My conceptual problem is that I= never=20 know which way to swing around - at each transition one has to make=20 an=C2=A0arbitrary decision=C2=A0between a low or high frequency=20 spike...
=C2=A0
=C2=A0
All the best,
Markus (DF6NM)
=C2=A0
=C2=A0

Sent: Saturday, November 14, 2015 9:47 PM
Subject: Re: LF: Ramped BPSK

Hi Andy,

I was about to solder a dpdt relay across a= =20 transformer until I saw your
posting.=C2=A0 The DDS here is the 9851 an= d the=20 40 bits are loaded serially.
If bits 35-39 are changed from 00000 to 000= 10=20 the phase will change by
180 degrees and so the soldering iron can be=20 switched off?

An AD9852 would spare me the humiliation of being a=20 significant
part of a mHz off QRG, but these chips seem hard to get.=C2= =A0=20 Markus was
right about the resolution. The DDS is clocked at 10 MHz with= =20 the
x6 multiplier. The output is then divided by 16.=C2=A0 The resolutio= n is=20 just
under 1 mHz and so the frequency error depends on the output=20 frequency.

73 Joe VO1NA



On Sat, 14 Nov 2015, Andy Tal= bot=20 wrote:

> Try the Anlaog Devices web site - www.analog.com
>
> I built my= own=20 PCB,=C2=A0=C2=A0 http://www.g4jnt.com/AD9852module.pdf=C2=A0=C2=A0=20 (PCBs are no
> longer available for that, though).=C2=A0 That particu= lar=20 DDS is a bit out of
> date now.=C2=A0 I use it=C2=A0 for this job as = I=20 have a few modules left, and it is
> one of the few devices=C2=A0 wit= h=20 both a 48 bit frequency setting register and
> amplitude=20 programmability.
>
> Andy=C2=A0 G4JNT
>
> On 14 Nov= ember=20 2015 at 19:20, Paul Nicholson <vlf0403@abelian.org>=20 wrote:
>
>>
>> With sufficiently brief phase steps,= =20 those discrete sidebands
>> will fall outside the loading coil=20 bandwidth and be well
>> attenuated.
>>
>> But, = does=20 that bring back the audible clicks from the PA
>> and=20 coil?
>>
>> I'm keen to have a play with these DDS=20 chips.=C2=A0 Is there a
>> recommended evaluation=20 board?
>>
>&g= t; --
>> Paul Nicholson
>>=20 --
>>
>>
>


--001a11442706f51f540524994799--