Return-Path: X-Spam-DCC: paranoid 1102; Body=2 Fuz1=2 Fuz2=2 X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on lipkowski.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DNS_FROM_AHBL_RHSBL, HTML_40_50,HTML_MESSAGE autolearn=no version=3.1.3 Received: from post.thorcom.com (post.thorcom.com [195.171.43.25]) by paranoid.lipkowski.org (8.13.7/8.13.7) with ESMTP id t61J0oQY014858 for ; Wed, 1 Jul 2015 21:00:51 +0200 Received: from majordom by post.thorcom.com with local (Exim 4.14) id 1ZANDE-0003rD-PK for rs_out_1@blacksheep.org; Wed, 01 Jul 2015 19:58:24 +0100 Received: from [195.171.43.32] (helo=relay1.thorcom.net) by post.thorcom.com with esmtp (Exim 4.14) id 1ZANDE-0003r2-Cj for rsgb_lf_group@blacksheep.org; Wed, 01 Jul 2015 19:58:24 +0100 Received: from mail-wg0-f45.google.com ([74.125.82.45]) by relay1.thorcom.net with esmtps (TLSv1.2:AES128-GCM-SHA256:128) (Exim 4.85) (envelope-from ) id 1ZANDC-0005dn-Bz for rsgb_lf_group@blacksheep.org; Wed, 01 Jul 2015 19:58:23 +0100 Received: by wgck11 with SMTP id k11so44620936wgc.0 for ; Wed, 01 Jul 2015 11:58:21 -0700 (PDT) X-DKIM-Result: Domain=gmail.com Result=Good and Known Domain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; bh=4TZgwc91msP7cDXM05WVdT1m8LOlEG68lWXzH3F03pc=; b=MwOWSr/IKcOv+osclckICebnnb9+aSOTdiDTtawYIfqLbQGo1UyTCG1FOqfF46u/xp 5QdQYJItJUGVyTb2ZIleaAYDuvfTemdjLO734SMtlVzIiYf4JigN4I+vJs7sO7pNPiFJ 6l4g8rF4C3gThb3I1BEpq5mq6PjhRbfNn9MTkxx7ge1slddwhX8iZodun9iYs8nK7MQe pWIyG952li4VaLAklskV1uc+oEAFZrmG2Zp+CIPE/iivvPs7V1rdBnfAVDPXN81hGVpR wxloP+pTvJ3NKmbN24CcE3KWMAN9NxroNnRHuc9SMSAD6gGSegn5NWjCyk///6UZURkB kF8w== MIME-Version: 1.0 X-Received: by 10.194.47.164 with SMTP id e4mr50214557wjn.157.1435777101437; Wed, 01 Jul 2015 11:58:21 -0700 (PDT) Received: by 10.28.28.7 with HTTP; Wed, 1 Jul 2015 11:58:21 -0700 (PDT) In-Reply-To: References: <7D577AEFBA43411C807FDDFBCF90CCC0@AGB> Date: Wed, 1 Jul 2015 19:58:21 +0100 Message-ID: From: Andy Talbot To: rsgb_lf_group@blacksheep.org X-Scan-Signature: d2a449809c9c1ff1983612d049372878 Subject: Re: LF: what causes this on wspr Content-Type: multipart/alternative; boundary=047d7b86d4941b9ec80519d4e81f X-SA-Exim-Scanned: Yes Sender: owner-rsgb_lf_group@blacksheep.org Precedence: bulk Reply-To: rsgb_lf_group@blacksheep.org X-Listname: rsgb_lf_group X-SA-Exim-Rcpt-To: rs_out_1@blacksheep.org X-SA-Exim-Scanned: No; SAEximRunCond expanded to false X-Scanned-By: MIMEDefang 2.56 on 10.1.3.10 Status: O X-Status: X-Keywords: X-UID: 3598 --047d7b86d4941b9ec80519d4e81f Content-Type: text/plain; charset=UTF-8 Its more than just PLL settling time. That could be controlled by suitable choice of loop bandwidth. At least I think it is. It could be part of the PLL's own internal VCO calibration when it is reprogrammed. First discovered this using the LMX2541 to generate WSJT modes on beacons. But found a suitable work around on that chip. Designers of the U3 with its Si5xxxx family device haven't even acknowledged the problem , don't have teh test equipment to measure it, won't take advice, and teh chip is poorly documented anyway - unlike TI's products. See next months RadCom (August issue) where I discuss in a lot more depth the problems using Fract-N synths with internal VCOs when generating MFSK modes and why these occur. Andy On 1 July 2015 at 19:48, Graham wrote: > I don't think its stability Andy , could be step response and > settling time , the new U3 kit uses a PLL and produces , what was > thought to be key click's but is PLL settling time , out of lock > detectors would normally inhibit output , but for a phase cont system > .. there's a conflict of interests , no problem keying Opera as its > a single tone , fixed frequency , but the mfsk modes have problems > associated .. the original used DSS > > , PLL's may be the wrong way to go I think for a exciter , > where large step changes in frequency are commanded , after all , > we know why DDS's where first devised : ) > > G, > > *From:* Andy Talbot > *Sent:* Wednesday, July 01, 2015 6:22 PM > *To:* rsgb_lf_group@blacksheep.org > *Subject:* Re: LF: what causes this on wspr > > Yep - I missed the fact it was over a minute long . > The sidebands are 12Hz (not 8Hz as I said before) which seems a bit close > for any synth instability. Nothing is that slow surely. > > So a bit of a mystery in that case. Still reckon it looks like CW > though. Hard on -off keing generates a spectrum at harmonics of the > clock frequency > > > > Andy > > > On 1 July 2015 at 17:58, Graham wrote: > >> Hi Andy >> >> Problem there is it lasts , what seems to be the full duration >> of the data phase [ phase as a change from cw to data .. etc ] >> >> wspr via a ssb rig , overdriving usually produces , harmonic >> side bands , 1000 , 2000 Hz etc Mains Hum 50/100/150 etc >> >> The power distribution looks like a FM signal , that would also >> account for the equal distribution about the centre and the >> extended group of side bands to the right .. >> >> I would take shot at a kit using either a PLL or one of >> the clock pulse systems .. with timing jitter ? >> >> 73 -G, >> >> *From:* Andy Talbot >> *Sent:* Wednesday, July 01, 2015 5:33 PM >> *To:* rsgb_lf_group@blacksheep.org >> *Subject:* Re: LF: what causes this on wspr >> >> Fast CW ident perhaps ? >> The spectral lines look to be about 8Hz apart so that makes it 10 WPM or >> thereabouts >> >> Andy 'jnt >> >> >> On 1 July 2015 at 17:24, Graham wrote: >> >>> what causes this on wspr >>> >>> This takes some doing ...... but how to do it ? >>> >>> G, >>> >> >> > --047d7b86d4941b9ec80519d4e81f Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Its more than just PLL settling time. =C2=A0 That could be= controlled by suitable choice of loop bandwidth.=C2=A0 At least I think it= is.=C2=A0
It could be part of the PLL's own internal VCO calibrati= on when it is reprogrammed.=C2=A0 First discovered this using the LMX2541 t= o generate WSJT modes on beacons.=C2=A0 But found a suitable work around on= that chip.=C2=A0 Designers of the U3 with its Si5xxxx family device haven&= #39;t even acknowledged the problem , don't have teh test equipment to = measure it, won't take advice, and teh chip is poorly documented anyway= - unlike TI's products.

=C2=A0See next months RadCo= m (August issue) where I discuss in a lot more depth the problems using Fra= ct-N synths with internal VCOs when generating =C2=A0MFSK modes and why the= se occur.

Andy


On 1 July 2015 at 19= :48, Graham <g8fzk@g8fzk.fsnet.co.uk> wrote:
I don't think=C2=A0 its=C2=A0 stability Andy =C2=A0,=C2=A0 could= =C2=A0 be=20 step=C2=A0 response and=C2=A0 settling=C2=A0 time ,=C2=A0=C2=A0 the=C2=A0= =20 new=C2=A0 U3 kit=C2=A0=C2=A0 uses=C2=A0 a=C2=A0 PLL and produces=C2=A0 , wh= at=20 was thought to=C2=A0 be=C2=A0 key=C2=A0 click's=C2=A0 but=C2=A0=20 is=C2=A0=C2=A0PLL=C2=A0=C2=A0=C2=A0settling time ,=C2=A0 out of lock=C2=A0= =20 detectors=C2=A0 would=C2=A0 normally inhibit=C2=A0 output , but for a=C2=A0= =20 phase cont=C2=A0 system .. there's=C2=A0 a=C2=A0 conflict of interests = , no=20 problem=C2=A0 keying=C2=A0 Opera=C2=A0 as=C2=A0 its a=C2=A0 single=C2=A0 to= ne ,=20 fixed=C2=A0 frequency , but the=C2=A0 mfsk=C2=A0 modes=C2=A0 have=C2=A0=20 problems=C2=A0 associated=C2=A0 ..=C2=A0 the=C2=A0 original=C2=A0 used=C2= =A0 DSS=20
=C2=A0
=C2=A0,=C2=A0PLL's=C2=A0=C2=A0=C2=A0may=C2=A0 be =C2=A0 the=C2=A0= =20 wrong=C2=A0 way to=C2=A0 go I think for a=C2=A0 exciter , where=C2=A0 large= =20 step=C2=A0 changes=C2=A0 in frequency=C2=A0 are=C2=A0 commanded =C2=A0,=C2= =A0=20 after=C2=A0 all=C2=A0 ,=C2=A0 we=C2=A0 know=C2=A0 why=C2=A0 DDS's=C2=A0= =20 where=C2=A0 first=C2=A0 devised : )=C2=A0
=C2=A0
G,

Sent: Wednesday, July 01, 2015 6:22 PM
Subject: Re: LF: what causes this on wspr

Yep - I missed the fact it was over a minute long .=20
The sidebands are 12Hz (not 8Hz as I said before) which seems a bit cl= ose=20 for any synth instability.=C2=A0 Nothing is that slow surely.

So a bit of a mystery in that case. =C2=A0 =C2=A0Still reckon it looks= like=20 CW though. =C2=A0 =C2=A0Hard on -off keing generates a spectrum at harmonic= s of=20 the clock frequency



Andy


On 1 July 2015 at 17:58, Graham <g8fzk@g8= fzk.fsnet.co.uk> wrote:
Hi Andy
=C2=A0
Problem there=C2=A0 is=C2=A0 it=C2=A0 lasts=C2=A0 , what=C2=A0=20 seems=C2=A0 to=C2=A0 be=C2=A0 the=C2=A0 full=C2=A0 duration=C2=A0 of the= =C2=A0=20 data=C2=A0 phase=C2=A0 [ phase as=C2=A0 a change=C2=A0 from=C2=A0 cw=C2= =A0 to=20 data .. etc ]
=C2=A0
wspr=C2=A0 via a=C2=A0 ssb=C2=A0 rig ,=C2=A0 overdriving=C2=A0=20 usually=C2=A0 produces=C2=A0 , harmonic=C2=A0 side=C2=A0 bands ,=C2=A0=C2= =A0=20 1000=C2=A0 , 2000=C2=A0=C2=A0 Hz etc=C2=A0 Mains=C2=A0 Hum=C2=A0=20 50/100/150=C2=A0 etc=C2=A0
=C2=A0
The=C2=A0 power=C2=A0 distribution=C2=A0 looks like a=C2=A0 FM signa= l=20 ,=C2=A0 that=C2=A0 would=C2=A0 also=C2=A0 account=C2=A0 for the=C2=A0=20 equal=C2=A0=C2=A0=C2=A0 distribution=C2=A0=C2=A0 about=C2=A0 the=C2=A0=20 centre=C2=A0 and the=C2=A0 extended=C2=A0 group=C2=A0 of=C2=A0 side=C2=A0= =20 bands=C2=A0 to=C2=A0 the=C2=A0 right ..
=C2=A0
I would=C2=A0 take=C2=A0=C2=A0 shot=C2=A0 at=C2=A0 a=C2=A0 kit=C2=A0= =20 using=C2=A0=C2=A0 either=C2=A0 a=C2=A0 PLL=C2=A0=C2=A0=C2=A0 or=C2=A0=C2= =A0=20 one=C2=A0 of the=C2=A0 clock=C2=A0 pulse=C2=A0 systems=C2=A0 .. with=C2= =A0=20 timing=C2=A0 jitter=C2=A0 ?
=C2=A0
73 -G,

Sent: Wednesday, July 01, 2015 5:33 PM
Subject: Re: LF: what causes this on wspr

Fast CW ident perhaps ?=20
The spectral lines look to be about 8Hz apart so that makes it 10 WP= M or=20 thereabouts

Andy =C2=A0'jnt


On 1 July 2015 at 17:24, Graham <g8fzk@= g8fzk.fsnet.co.uk> wrote:
what causes this=C2=A0 on wspr
=C2=A0
This=C2=A0 takes=C2=A0 some=C2=A0 doing=C2=A0 ...... but=C2=A0=20 how=C2=A0 to=C2=A0 do=C2=A0 it=C2=A0 ?
=C2=A0
G,



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