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Message-ID: <D9D2BC233E6248D095857032DE0B8974@JimPC>
From: "James Moritz" <james.moritz@btopenworld.com>
To: <rsgb_lf_group@blacksheep.org>
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In-Reply-To: <003801cbb33e$8b59e620$0401a8c0@xphd97xgq27nyf>
Date: Thu, 13 Jan 2011 17:31:32 -0000
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Subject: LF: Re: FET RDS
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Dear Mal, Andy, LF Group,

There is a trade-off in construction of MOSFETs - basically, for a given 
area of silicon,  higher BVdss requires a thicker active region of the 
MOSFET with higher on resistance. You can reduce Rdson by using a greater 
chip area, but that means higher capacitances, increased cost, etc. So you 
can't have your cake and eat it.

In Andy's breadboard circuit, there is a mismatch between the available 
MOSFET type and the available PSU voltage - the 500V BVdss is a bit too high 
for a 60V DC supply - the peak voltage in an ideal class E is 3.56 x Vdc, 
perhaps you would allow 5 x Vdc for safety. 300V BVdss mosfets seem a bit 
thin on the ground, so more efficient schemes might be to increase Vdc to 
about 100V, or reduce it to about 40V and use lower Rdson 200V mosfets.

Cheers, Jim Moritz
73 de M0BMU