Message-ID: <002d01cbb3d3$ded8e9a0$0401a8c0@xphd97xgq27nyf>
From: "mal hamilton" <g3kevmal@talktalk.net>
To: <rsgb_lf_group@blacksheep.org>
References: <003801cbb33e$8b59e620$0401a8c0@xphd97xgq27nyf> <D9D2BC233E6248D095857032DE0B8974@JimPC> <004001cbb349$8b4ec190$0401a8c0@xphd97xgq27nyf> <4D2F705F.7020804@iup.uni-heidelberg.de>
Date: Fri, 14 Jan 2011 10:14:46 -0000
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Subject: Re: LF: Re: Re: FET RDS
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Stefan
At this sort of measured efficiency you would need very accurate calib=
rated
measuring equipment.
Figures of 96% are only possible with MAGIC FETS, RDS 0.0 and PA coils=
 with
wire resistance of 0
Measure DC input V*I (watts) on load, then RF output into a dummy load=
 I
squared R (watts) subtract one result from the other ie loss and calcu=
late %
efficiency.
Instrument accuracy could be out of calibration by several percent.
73 de mal/g3kev

----- Original Message -----
From: "Stefan Sch=E4fer" <schaefer@iup.uni-heidelberg.de>
To: <rsgb_lf_group@blacksheep.org>
Sent: Thursday, January 13, 2011 9:36 PM
Subject: Re: LF: Re: Re: FET RDS


> My LF 1 kW class E PA i using a single IRFP360 at > 96 % efficiency=
 (at
> Z=3DR=3D50 Ohm of course). The driver is a ICL7667. The supply volta=
ge is 80
> VDC. That's not a dream ;-)
>
> Stefan/DK7FC
>
> Am 13.01.2011 18:44, schrieb mal hamilton:
> > Jim
> > What you say is correct but it is virtually impossible to achieve=
 the
90%
> > plus efficiency claimed by some. The FET required in practice is=
 not
> > available and these high efficiencies are only theoritical.
> > I have found this in practice ie 80% if you are lucky on a good da=
y
> > mal/g3kev
> >
> >
> > ----- Original Message -----
> > From: "James Moritz"<james.moritz@btopenworld.com>
> > To:<rsgb_lf_group@blacksheep.org>
> > Sent: Thursday, January 13, 2011 5:31 PM
> > Subject: LF: Re: FET RDS
> >
> >
> >
> >> Dear Mal, Andy, LF Group,
> >>
> >> There is a trade-off in construction of MOSFETs - basically, for=
 a
given
> >> area of silicon,  higher BVdss requires a thicker active region=
 of the
> >> MOSFET with higher on resistance. You can reduce Rdson by using=
 a
greater
> >> chip area, but that means higher capacitances, increased cost, et=
c. So
you
> >> can't have your cake and eat it.
> >>
> >> In Andy's breadboard circuit, there is a mismatch between the ava=
ilable
> >> MOSFET type and the available PSU voltage - the 500V BVdss is a=
 bit too
> >>
> > high
> >
> >> for a 60V DC supply - the peak voltage in an ideal class E is 3.5=
6 x
Vdc,
> >> perhaps you would allow 5 x Vdc for safety. 300V BVdss mosfets se=
em a
bit
> >> thin on the ground, so more efficient schemes might be to increas=
e Vdc
to
> >> about 100V, or reduce it to about 40V and use lower Rdson 200V mo=
sfets.
> >>
> >> Cheers, Jim Moritz
> >> 73 de M0BMU
> >>
> >>
> >>
> >>
> >
>