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Message-ID: <5.1.0.14.0.20021105175108.00a98498@gemini.herts.ac.uk>
Date: Tue, 05 Nov 2002 18:53:16 +0000
To: rsgb_lf_group@blacksheep.org
From: "James Moritz" <j.r.moritz@herts.ac.uk>
In-reply-to: <004901c281e8$7b4c7800$b1a3edc2@oemuser>
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Subject: Re: LF: Loop preamplifier
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Dear Urban, LF Group,

At 21:51 01/11/2002 +0100, you wrote:
>The following items have been changed:
>
>The 2N3819:s are replaced by high current FET:s BF246C (the same pinout).
>R3 and R4 are decreased from 2.2k to 270ohms
>The source lead in each FET is broken up and 150 ohm (see below though) in 
>parallel with 0.1uF are inserted.
>The leads between the drains of the FET:s to the bases of the 2N2222:s are 
>broken up and 47k in parallell with 0.1 uF are inserted.
>R5 is decreased from 1k to 180 ohms.
>
As has been discussed on the reflector before, there are a number of design 
flaws in the G3LNP preamp design - Urban's mods deal with the problem of 
the loosely specified Idss and mismatch between the input FETS, and the low 
bias current in the output follower - a further problem is the way the 
output followers are biased.

At DC the 2 emitters are effectively connected together via the output 
transformer. In order to get equal current in each output transistor, the 
base-emitter voltages must be exactly the same. A small mismatch in Vbe 
will cause a large change in Ic; eg. a 20mV  mismatch will result in a 
roughly 2:1 ratio in the collector currents, 60mV will result in 10:1 
ratio. Since the base voltages are determined by the FET characteristics, 
even if it is possible to set up the FET bias for exactly equal voltages on 
the output transistor bases, and select output transistors with accurately 
matched Vbe, a few degrees of temperature change will cause the collector 
currents to drift severely. In practice this means that the amplifier will 
always be working with one output transistor effectively cut off, so it 
will actually be working as a single-ended amplifier instead of a balanced 
push-pull amplifier.

The 47k resistors in series with the output transistor bases that Urban has 
added will go some way to improving this situation, but a better way is to 
do the following: Remove R5 and C4 and connect the centre tap of the 
transformer to ground. Then break the connection between each emitter lead 
and the transformer, and insert a resistor of, say, 330R bypassed by a 100n 
or larger capacitor in series with each emitter. Now, the two output 
transistors are independently biased, and will have fairly accurately 
matched currents provided the FET drain voltages are within about +/- 1V of 
each other. With the FET bias set for 6V on each drain, the emitter current 
will be about 16mA in each transistor. Having the output stage better 
balanced should reduce the distortion.

Cheers, Jim Moritz
73 de M0BMU