Message-ID: <15264.200103281753@gemini>
From: "James Moritz" <j.r.moritz@herts.ac.uk>
Organization: University of Hertfordshire
To: rsgb_lf_group@blacksheep.org
Date: Wed, 28 Mar 2001 18:58:17 +0000
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Subject: LF: <Tech>BPSK modulation - PLL
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Dear Rick, LF group,

Suppose the PLL is phase locked to the input signal, and suddenly 
a 180degrees phase transition occurs at the input. There would 
then be an error signal in the loop, which would force the relative 
phase of the output to change until it matched the input signal 
again. The phase would have to change in a continuous fashion 
since the loop filter would prevent the VCO tuning voltage from 
changing discontinuously - presumably, you could control the rate 
at which the phase changed by altering the loop filter time 
constants. 

But I can see a problem - what will the PLL do at the instant the 
phase changes? as far as the phase detector is concerned, a 
sudden 180degree phase change could mean either a lead of 180 
degrees or a lag of 180degrees. The error between input and 
output phases could be corrected either by increasing the VCO 
frequency until the output phase "catches up" with the input, or 
decreasing it until it "slows down" to match the input. The output 
phase could shift in either direction, although the end result would 
always be to match the input phase. The PLL texts call the period 
that the circuit is achieving the phase-locked condition the "capture 
transient", and each capture transient is an individual, depending 
on the type of phase detector, the timing of the input transient 
relative to the VCO output phase, residual phase errors and noise 
in the loop, etc, etc. The output phase can go through a much more 
complicated trajectory than the input.

Therefore, each output phase transition would be different as well 
as gradual; presumably, this would add a noise-like element to the 
sidebands of the signal. Hopefully, there would be an equal number 
of "up" transitions as "down" transitions, otherwise the mean 
frequency of the output would be different to that of the input. What 
effect all this would have on the bandwidth, and communications 
efficiency of the signal, I don't know, but for a simple circuit, 
behaviour would be quite complex.

Cheers, Jim Moritz
73 de M0BMU