Message-ID: <3A7EDE6C.D537F511@bellatlantic.net>
Date: Mon, 05 Feb 2001 12:10:05 -0500
From: "Andre' Kesteloot" <akestelo@bellatlantic.net>
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To: rsgb_lf_group@blacksheep.org
Cc: "lf, AMRAD" <lf@amrad.org>
Subject: Re: LF: PLL / Loop antennas
References: <5501.200102051521@gemini>
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James Moritz wrote:

> Re: Phase locked loops; Andre wrote-
>
> >"...the implementation of figure 8.6 has a resolution of 0.35
> > degrees.
>
> A fixed error in frequency means a constantly increasing error in phase. Suppose a phase locked loop has a reference frequency of 1MHz exactly, and is trying to lock a VCO which is running at 1.000001MHz. If both reference and VCO have the same phase at one particular moment, one cycle later the VCO will be leading in phase by 1e-6 cycles, or 0.00036 degrees, which may well be lost in the noise and other errors at the phase detector output. But after 2 cycles it will be 0.00072 degrees, after about 972 cycles, the accumulated phase error will be 0.35 degrees, and after 1000000 cycles it will be 360 degrees. However small the frequency error, over a long enough time the phase error will increase to the point where it becomes the dominant signal in the feedback loop - probably a rather small fraction of a second in the above example.

Yes Jim, I agree entirely.
That is why my original posting mentioned that whenever we insert a divider-by-N between VCO and phase detector, we must keep in mind that the VCO can drift N times more than the phase angle at the phase detector/comparator. That error may, or may not be significant.
73
Andre'