Message-ID: <002201c119fe$589f3160$e10a97d4@oemcomputer>
From: "Johan Bodin" <sm6lkm.jbeab@swipnet.se>
To: rsgb_lf_group@blacksheep.org
Subject: LF: SV: LF Receivers
Date: Tue, 31 Jul 2001 23:20:41 +0300
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Hi Andy

Your new RX design is interesting!

Is the BFO phase locked to "an exact integer kHz"? If so, the DDS LO
will be the only source of "odd steps". Clocked at 10MHz, it will produce
an LO signal that is a multiple of 2.328306437... mHz (assuming 32-bit
phase accumulator (or do you use the 48-bit creatures?)). This is a quite
unpleasant number if the RX is to be used for *ultra* narrowband work.

A (more complicated) alternative is to clock the DDS from a 10.7374... MHz
VCXO to get 2.50000000... mHz steps. The VCXO can be phase locked to
the frequency standard by using a second DDS chip as a non-integer divider.
For example, if the divider DDS is set to a phase increment of 400,000,000
the output will be exactly on 1 MHz which can be phase compared with a
divided-down 1MHz signal from the standard for PLLing the VCXO.

Hmm... 

Another (less complicated) alternative is that both (all) potential ends of a QSO
agree on the same DDS clock frequency, say 10MHz or a (sub-)multiple thereof :~)

73
Johan SM6LKM