Message-ID: <001201c11de7$6051a9a0$916c97d4@oemcomputer>
From: "Johan Bodin" <sm6lkm.jbeab@swipnet.se>
To: rsgb_lf_group@blacksheep.org
Subject: SV: LF: Harmonic sampling (Was: Decimation)
Date: Sun, 5 Aug 2001 22:46:14 +0300
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Paul,

>An undersampling system needs some kind of sample & hold circuit. IIRC from
>digital audio, the aperture time should be less than T/10 (T=sampling
>period) in order to keep the high frequency rolloff below 1 dB.

Yes, the figures sounds reasonable.


>So if we assume a hypothetical 300 kHz sampling rate (for 0 .. 140 kHz BW),
>the aquisition time should be less than 300 ns, which should not be too hard to
>implement:-). Since the hold time is about 170 us (6 kHz), we are talking
>about 1:500 aquisition/hold time ratios, which can be a problem due to hold
>time leakage.

Yes, the 1:500 ratio could turn the S/H "droop rate" into a problem.
I was thinking about using a cheap 74HC4066 or similar analog switch as sampling
gate but after giving it a second thought I realised that it is probably out of the question
due to the high "charge injection" from the control pin to the switch i/o pins.
The hold cap' has to be quite small in order to meet the acquisition time requirement
so the control pulse leakage will probably upset things... Assuming S/H driver source
resistance + switch R-on = 50 ohms, C has to be about 10nF for -3dB at 300kHz but...
At an aquisition/hold time ratio of 1:500, C must be <= 20pF. Among other things, this
calls for a buffer amplifier having almost zero bias current :~)

Do you have any suggestion for a hombrew S/H circuit? Diode ring gate? Ready made
S/H chip? I have no experience of building fast S/H circuits.


>By adding dithering noise, low and medium frequency tones could be reproduced
>well below -100 dB, when the teoretical limit for a 16 bit system would be -96 dB.

Yes, isn't it funny...The system performance can sometimes be improved by ADDING
noise! The dithering noise spectrum has to be outside the wanted passband of course.


>If some super-selective front end is used (say 250 Hz bandwidth) in the LF
>receiver, the digital signal may contain signal related quantisation noise,
>thus some form of dither noise may be required. However, if the analog
>bandwidth is larger, I guess that the band noise may be used as dither noise. 

Yes.

Steve VK2ZTO did some extreme narrowband experiments on longwave using a 1-bit
ADC. I think it was a simple comparator hooked on the RX audio output. Dithered by natural
band noise, the signal appeared to have many bits of resolution after the decimation.

Fs=6kHz seems like a good choice. The selected Fs harmonic should be just outside
the band of interest (lowest acceptable beat note) and the preselector BW (-many dB!)
must be less than Fs/2. Pse correct me if I'm wrong.


>>From this description, it appears as if this device is actually a 13 bit
>flash ADC and the three extra bits are generated by the Fs/8 downsampling
>:-).

Right. It's not a true 16-bit ADC. It is some kind of combination of a sigma-delta
with 5-bit flash & 5-bit feedback and a 12-bit pipelined ADC.

Some data:
- Fs <= 20MHz
- 1 MHz signal BW
- SNR 89 dB
- THD -98dB
- SFDR 100dB
- Equiv. input noise 0.6 LSB
- Stopband attenuation 85 dB

Unfortunately, my preliminary data sheet doesn't tell the ENOB (effective number of bits).

I actually have two of these chips and a HSP50016 DDC too. I hope that I someday will
find some time to play with them...

Anyway, the harmonic sampling idea is *very* appealing.

73
Johan SM6LKM